Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract: One aspect of the present invention is to provide a method for compensating a system duty cycle of a system clock signal. The method in one embodiment comprises the following steps: locking a duty cycle center of the system duty cycle by a delay lock loop; detecting a current system duty cycle of the system clock signal; determining a duty cycle correction amount, wherein the duty cycle correction amount is a gap of the current system duty cycle from a target duty cycle; and changing a polarity of an input reference clock signal according to whether the duty cycle correction amount exceed a threshold amount or not.

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A circuit is configured to generate periodic control signals including at least two mutually phase-shifted control signals. The circuit includes a plurality of generator circuits, where a separate generator circuit is provided for each control signal output by the circuit. Each generator circuit includes a phase value memory configured to store a phase value, where the phase value defines a phase shift. Each generator circuit includes an activation input and, in response to application of an activation level to the activation input, is configured to initiate a generation of a control signal which is phase-shifted by an amount defined by the phase value. The activation inputs of the generator circuits are connected together to an activation circuit for outputting an activation level to the generator circuits simultaneously.

Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.

Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract: A signal transmission circuit includes an isolation circuit, first and second grounded gate circuits, first and second MOS transistors, and a comparator. The isolation circuit such as a thin-film transformer outputs complementary first and second output signals, based on an input signal. The first and second grounded gate circuits receive and amplify the first and second output signals, respectively. The first and second MOS transistors are connected between a power supply node and the first and second grounded gate circuits, respectively, for adjusting the first and second output signals. The comparator compares output from the first grounded gate circuit with output from the second grounded gate circuit.

Abstract: A voltage reference circuit includes a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground. A second depletion-mode PMOS transistor is coupled to the first enhancement PMOS transistor to form a feedback circuit. A first resistive device is coupled between the voltage supply and the second depletion-mode PMOS transistor, and a second resistive device is coupled between the second depletion-mode PMOS transistor and the ground. A bias circuit is coupled to a gate of the first enhancement-mode NMOS transistor. The first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region. A first reference voltage across the first resistor and a second reference voltage across the second resistor are configured to be independent of the magnitude of the voltage supply and have low temperature drift.

Abstract: The reconfigurable Nth-order filter includes a CCII adopting active current division networks for implementing the proposed filter. This digitally programmable second generation current conveyor leads to wide control of filter coefficients for reconfiguration of the filter. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 ?m CMOS process.

Abstract: The present document discloses a driver circuit for the high side switch of a half bridge at ultra-high voltage. The half bridge comprises the high side switch coupled to an input voltage Vin and to a midpoint of a low side switch. The driver circuit comprises a control signal generation unit generating a stream of control pulses and a control logic generating a gate voltage for the high side switch using a supply voltage Vcc based on the control pulses, a supply voltage capacitor generating the supply voltage Vcc, and a decoupling capacitor coupled on a first side to the control signal generation unit and on a second side to the control logic, to the midpoint of the half bridge via a first charging switch, and to the supply voltage capacitor via a second charging switch.

Abstract: The application concerns a surface mount module adapted for transfer of a microwave signal between the module and a motherboard, the module comprising a substrate with a first microstrip conductor and a second microstrip conductor, wherein the two conductors are connected with a connection through the module. The module is distinguished in that the connection comprises the first microstrip conductor connected to a foil of electrically conducting material coated on the first side, the foil being surrounded by electrically conducting trenches running through the substrate from the first side to the second side forming a substrate integrated waveguide, wherein the trenches on the second side surrounds a second foil of electrically conducting material coated on the second side of the substrate and connected the second microstrip conductor. The application also concerns a coupling arrangement.

Abstract: An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

Abstract: A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS and NMOS transistors, in which the input signal to be frequency divided is supplied to the body of the PMOS and/or NMOS transistors. The input signal may be coupled to the PMOS and/or NMOS transistors through capacitive or inductive coupling. The input signal to the PMOS and/or NMOS transistors may be generated by a voltage controlled oscillator circuit. With the frequency divider circuit having inputs signals coupled to the body of the PMOS and/or NMOS transistors supply voltages as low as 0.5 Volts may be possible.

Abstract: An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.

Abstract: A power detection circuit according to the present invention includes a variable frequency oscillator 2 for oscillating a local oscillator frequency, a mixer 1 for receiving the local oscillator frequency and a detection signal and converting a frequency of the detection signal using the local oscillator frequency, a complex bandpass filter 3 for limiting a bandwidth of the detection signal whose frequency is converted to a predetermined bandwidth, and an energy detection circuit 4 for detecting power of the predetermined bandwidth based on an output from the complex bandpass filter 3. The local oscillator frequency is set so that the predetermined bandwidth of the detection signal whose frequency is converted is in a frequency range having low 1/f noise. According to the present invention, it is possible to provide a power detection circuit with high speed and high sensitivity.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.