Abstract: A device includes a first hybrid, where a first input of the first hybrid is coupled to an output of a first amplifier configured to receive a first input signal. A first input of a second hybrid is coupled to an output of a second amplifier configured to receive a second input signal. The device includes a first phase shifter configured to receive the first input signal and a second phase shifter configured to receive the second input signal. An output of the first phase shifter is coupled to an input of a third amplifier, and an output of the third amplifier is coupled to a second input of the second hybrid. An output of the second phase shifter is coupled to an input of a fourth amplifier, and an output of the fourth amplifier is coupled to a second input of the first hybrid.

Abstract: A semiconductor device comprises a plurality of transistor mismatch circuits formed on a semiconductor wafer; and a characterization circuit formed on the semiconductor wafer. The characterization circuit is coupled to receive input provided by the absolute value circuits simultaneously which themselves receive inputs from the mismatch circuits simultaneously and is configured to output a standard deviation of mismatch between transistors in the mismatch circuits.

Abstract: A circuit is provided for both boosting output current and providing short circuit protection in an integrated circuit such as an operational amplifier. In an embodiment, a current-boosting output stage with short-circuit protection includes six current sources and six transistors, where the the boosting of output current is achieved using positive feedback and the short circuit protection is achieved using negative feedback.

Abstract: Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.

Abstract: A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.

Abstract: A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.

Abstract: A system for regulating semiconductor devices may include a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT). The current regulator may regulate the currents by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT, or any combination thereof. The current profile may include one or more current values to be provided to a gate of the IGBT such that the current values are configured to limit the rate of collector voltage change to a first value. The current regulator may then send the one or more current values to a current source configured to supply the gate of the IGBT with one or more currents that correspond to the one or more current values.

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.

Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: The duty cycle corrector for correcting a system clock signal comprises a duty cycle detector and a duty cycle adjuster. The duty cycle detector is configured for detecting a system duty cycle of the system clock signal and generating the first control signal and the second control signal, wherein the first control signal and the second control signal are complementary to each other. The duty cycle adjuster comprises an inverter and the duty cycle adjuster is configured for delaying a change in an input status of the inverter and adjusting of the inverter in accordance with the first control signal and the second control signal.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: A ramp output control device includes a driver configured to receive at least two inputs from a microcontroller. The driver includes a time duration register configured to store a current clock count until a preset time duration is reached. The driver also includes a ramp output register configured to store a current output value at an output of the device. The driver also includes a calculation block configured to determine whether to increase the current output value at the output based on the at least two inputs.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.

Abstract: An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal.