Abstract: There is provided an analog-to-digital conversion apparatus that corrects digital data output from a plurality of analog-to-digital conversion units.

Abstract: An analog to digital converter includes a resistor-divider network including a plurality of resistors, an arbel channel circuit configured to generate a voltage sawtooth signal as an output, a dc-offset disposed to couple a node of the resistor-divider network and the arbel-channel circuit. The converter further includes a voltage reference circuit configured to generate a reference voltage, and a differential comparator configured to compare the voltage sawtooth signal with the reference voltage to produce a digital output signal corresponding to the voltage sawtooth signal. Method of converting an analog signal to a digital signal is also described.

Abstract: A device for positional and/or length determination comprising a carrier unit with an absolute magnetic length coding and a measuring unit that co-operates with the carrier measuring unit and can be displaced in relation to the latter. The measuring unit has a magnetic sensor unit (Sci, Sfi) and can be connected to an electronic evaluation unit (18 to 32) that is located downstream of the measuring unit. The elongated, rod-shaped carrier unit (10) is provided with one track of preferably radially magnetized length coding, a plurality of coding sections comprising periodic pole divisions is provided along the length coding and coding sections of a first polarity alternate with coding sections of a second polarity along the carrier unit, in such a way that a maximum of two coding sections of the same polarity lie directly adjacent to one another.

Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

Abstract: The invention discloses a method of embedding information for high quality restoration of a media signal (typically an audio-visual signal) in a lower quality version of the signal. To this end, the signal x is encoded using a high quality encoder (Q2). The code sequences z produced by the high quality encoder are mapped into code sequences y that are associated with a hypothetical lower quality encoder (Q1). The latter code sequences y are transmitted. A simple decoder will decode the received sequences y, and thus reproduce a low quality version of the signal. A more sophisticated decoder is arranged to inversely map the received code sequences y into the code sequences z, that were actually produced by the high quality encoder (Q2). The sophisticated decoder will thus reproduce a higher quality version of the same signal.

Abstract: A NICAM encoder (54) comprises a NICAM processor (82) and a front-end section (80,84) coupled to the NICAM processor. The front-end section is configured for operating with a system clock (68) that is integer divisible such that the system clock can be used by both the NICAM processor (82) and the front-end section (80,84).

Abstract: According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a first device. The method also includes sampling the analog signal using a second clock signal to generate a numeric representation of at least a portion of the analog signal. The frequencies of the first and the second clock signals differ from one another by a known amount. The method also includes communicating over the signal path the numeric representation for receipt by a second device. The signal path experiences loading and at least a majority of the loading of the signal path occurs between the sampler and the second device.

Abstract: In a semiconductor integrated circuit, serially inputted trimming data are sequentially written to plural memory cells in accordance with selection signals for trimming a bleeder resistor, making it possible to dispense with a data register for storing the trimming data, thereby saving layout area.

Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

Abstract: Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).

Abstract: The present invention relates to digital to analog converters, and especially but not exclusively to switched capacitor digital to analog converters (DACs) for digital audio signals. The present invention provides a switched capacitor DAC for converting a digital signal and comprising a feedback capacitor coupled between an input and an output of an operational amplifier; a charging capacitor and a switching arrangement arranged during a charging period to couple a first side of said charging capacitor to a first reference voltage or a second reference voltage dependent on said digital signal, the switching arrangement further arranged during said charging period to couple a second side of the charging capacitor to the second reference voltage or the first reference voltage in anti-phase to the reference voltage coupled to said first side of the charging capacitor; the switching arrangement further arranged during a settling period to couple said charging capacitor to said feedback capacitor.

Abstract: An analog-to-digital conversion arrangement for converting an analog input signal into a digital output signal with a most significant part and a least significant part comprises sample means for sampling the analog input signal, a plurality of coarse resolution analog-to-digital converters for converting the sampled analog input signal into a coarse digital signal representing the most significant part of the digital output signal, whereby the coarse resolution analog-to-digital converters are operated in an interleaved way. The analog-to-digital conversion arrangement further comprises a fine resolution analog-to-digital converter for converting the sampled analog input signal into a fine digital signal representing the least significant part of the digital output signal, based upon the coarse digital signal generated by any of said coarse resolution analog-to-digital converters.

Abstract: Disclosed is a data detector for detecting data placed on a bi-directional data channel having two nodes. The data on the data channel is a combination of data placed on the data channel at both nodes. The data detector at the first node compares data received from the data channel to multiple reference voltages. Which reference voltages are used for comparison is determined by the state of data placed on the data channel at the first node. By comparing the data from the data channel to more than one reference voltage data can be detected with a swing margin of about 50%, such that it is less affected by noise, power or other glitches than are conventional circuits. Methods of detecting data are also disclosed.

Abstract: An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.

Abstract: A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.

Abstract: A complex band-pass ?? AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

Abstract: I describe and claim an improved digital-to-analog conversion device and method. The device comprises a current supply circuit to generate a plurality of control currents responsive to a plurality of digital signals. An input voltage generating circuit is adapted to generate a plurality of input voltages responsive to the digital signals and the control currents. And a plurality of operational amplifiers is adapted to output a plurality of analog signals responsive to the input voltages.

Abstract: An analog to digital converter ADC is adapted for low power for use in an imaging array. The ADC is a digital inverter with feedback to convert an asynchronous ramp voltage to an output count at each crossing of a voltage threshold. A separate circuit generates a voltage ramp that is coupled through a capacitor to a photocurrent from a detector, generating an integrating voltage that is raised at a source follower circuit. The integrating voltage from the source follower circuit is converted to another voltage ramp and inverted at the ADC. A global count from an array of such ADCs is stored in a grey counter. The ADC is sufficiently power-efficient that each unit cell of an array of photo detectors can have its own ADC. Circuit and device-level embodiments are disclosed.

Abstract: A DA converter circuit is provided for use in a ?? AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.