Patents Examined by Patrick Wamsley
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Patent number: 7034727Abstract: A bandpass sigma-delta modulator using acoustic resonators or micro-mechanical resonators. In order to improve resolution at high frequencies, acoustic resonators or micro-mechanical resonators are utilized in a sigma-delta modulator instead of electronic resonators. The quantized output is fed back using a pair of D/A converters to an input summation device. In fourth order devices, the feed back is to two summation devices in series. Such a sigma-delta modulator is usable in a software defined radio cellular telephone system and in other applications where high-frequency and high-resolution A/D conversion is required.Type: GrantFiled: June 16, 2004Date of Patent: April 25, 2006Assignee: National University of SingaporeInventor: Yong-Ping Xu
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Patent number: 7030718Abstract: A tuning circuit for adjusting an oscillation frequency of an oscillator circuit. The tuning circuit comprises a film bulk acoustic wave resonator (FBAR) having a series resonance frequency and a parallel resonance frequency, and an inductor coupled in series or parallel with the film bulk acoustic wave resonator. The series connection of the inductor and FBAR decreases the series resonance frequency. The parallel connection of the inductor and the FBAR increases the parallel resonance frequency. The tuning circuit further comprises a varactor coupled in series or parallel with the inductor and the FBAR combination. The varactor tunes the oscillation frequency over the increased tuning range.Type: GrantFiled: August 9, 2002Date of Patent: April 18, 2006Assignee: National Semiconductor CorporationInventor: Dieter Scherer
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Patent number: 7030792Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.Type: GrantFiled: September 28, 2005Date of Patent: April 18, 2006Assignee: Texas Instruments IncorporatedInventor: Feng Chen
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Patent number: 7030785Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.Type: GrantFiled: January 7, 2005Date of Patent: April 18, 2006Assignee: Digital Fountain, Inc.Inventors: M. Amin Shokrollahi, Soren Lassen, Richard Karp
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Patent number: 7030795Abstract: An automatic gain control device (110) includes a peak detector (202) configured to receive a current output of an ADC (108) and to compare it to a previous output to produce a peak value. The automatic gain control device (110) also includes an out-of-range indicator (204) configured to receive an out-of-range signal if an input to the ADC exceeds the dynamic range of the ADC. The out-of-range indicator (204) increases the peak value if the out-of-range indicator (204) receives the out-of range signal. An error detector (206) is coupled to the out-of-range indicator (204) and the peak detector (202) and produces an error level that is the difference of an output of the out-of-range indicator (204) and a pre-selected target value. The pre-selected target value is chosen to attenuate interference signals that exceed the dynamic range of the ADC (108) but minimizes the attenuation of communication signals.Type: GrantFiled: May 17, 2005Date of Patent: April 18, 2006Assignee: Motorola, Inc.Inventors: David R. Saunders, Jeffrey D. Glaess, Robert K. Hansen, Arthur P. Helwig
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Patent number: 7026966Abstract: In a digital-to-analog converter including an integrated test circuit, a digital input and an analog output, a comparator (5) capable of being connected with the analog output (4) and including a connection (7) for a reference voltage source, a digital test connection (11) and a logic element is provided, the logic element being connected with the test connection (11) for emitting the digital value 0 or 1 as a function of the difference between the voltage at the analog output (4) and the reference voltage.Type: GrantFiled: May 13, 2002Date of Patent: April 11, 2006Assignee: Austriamicrosystems AGInventor: Helmut Theiler
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Patent number: 7023368Abstract: A digital-circuit return-to-zero device and method for digital-to-analog conversion is disclosed that uses an internal multiplexer alternatively selecting, or selecting in a scheduled fashion, digital input data and an expansion code. By the using the disclosed multiplexing process, where the expansion code is a null code, the usable analog spectrum of the digital-to-analog converter (DAC) extends beyond that of DACs. With the multiplexing process applied to a complementary interpolation process, the disclosed device is adapted for selective enhancement of the frequency spectrum proximate to the clock frequency. While extending the usable frequency spectrum beyond conventional DACs, the present invention, in its several embodiments, features low complexity and high portability relative to known response expansion solutions.Type: GrantFiled: August 31, 2004Date of Patent: April 4, 2006Assignee: Euvis, Inc.Inventors: Neng-Haung Sheng, Cheh-Ming Jeff Liu
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Patent number: 7019676Abstract: A current output type D/A converter for converting a digital signal into an analog signal comprises a control signal input terminal for receiving a control signal supplied from the outside, and an output load element having a switching mechanism for electrically connecting or disconnecting the output load element to/from an analog output node on the basis of the control signal applied to the control input terminal.Type: GrantFiled: June 10, 2004Date of Patent: March 28, 2006Assignee: Matsushita Electric Industrial Co, Ltd.Inventors: Heiji Ikoma, Koji Oka
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Patent number: 7015838Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.Type: GrantFiled: September 11, 2003Date of Patent: March 21, 2006Assignee: Xilinx, Inc.Inventors: Eric D. Groen, Charles W. Boecker
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Patent number: 7009545Abstract: A analog to digital converter is implemented in one chip. The one chip analog to digital converter includes an on-chip reference voltage generator for generating N number of reference voltages, N being a positive integer; and a conversion means for converting the inputted analog signal into a digital signal by using the reference voltages.Type: GrantFiled: December 31, 2003Date of Patent: March 7, 2006Assignee: Hynix Semiconductor Inc.Inventors: Young-Jae Cho, Seung-Hoon Lee
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Patent number: 7005944Abstract: A transmission line type noise filter, which is connectable between a direct current power supply and an electrical load component to pass a coming DC current while attenuating a coming AC current, includes a first conductor, a dielectric layer, a second conductor as a cathode, a first anode (12), and a second anode. The first and the second conductors and the dielectric layer serve as a capacitance forming portion. The thickness of the first conductor is selected to substantially restrict temperature elevation of the first conductor, which is caused by DC direct current flowing in the first conductor.Type: GrantFiled: July 31, 2003Date of Patent: February 28, 2006Assignee: NEC Tokin CorporationInventors: Satoshi Arai, Takayuki Inoi, Yoshihiko Saiki, Sadamu Toita
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Patent number: 7005946Abstract: A longitudinal mode resonator that includes a substrate and a bar that is suspended relative to the substrate. The bar is suspended such that it is free to expand and contract longitudinally in response to the application of an electric field across its thickness. The expansion and contraction of the bar achieves resonance in response to the field having a frequency substantially equal to the fundamental frequency of the bar.Type: GrantFiled: July 31, 2003Date of Patent: February 28, 2006Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Amy E. Duwel, David J. Carter, Mark J. Mescher, Mathew Varghese, Bernard M. Antkowiak, Marc S. Weinberg
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Patent number: 7002499Abstract: A digital-to-analog converter is disclosed, comprising an input/output circuit, a bistable circuit connected with the input/output circuit, a clock circuit connected with the input/output circuit and the bistable circuit, and a current generator circuit connected with the clock circuit. The clock circuit acts as a switch, providing current from the current generator either to the input/output circuit or to the bistable circuit. The digital input signal switches when the current generator provides current to the bistable circuit, and switching of the input signal is asserted at the output of the converter when the current generator provides current to the input/output circuit. Therefore, switching of a clock circuit signal, rather than switching of the digital input signal determines switching of the output signal, in order to reduce intersymbol interference of the converter associated with thermal hysteresis of some of the components of the converter.Type: GrantFiled: January 21, 2004Date of Patent: February 21, 2006Assignee: HRL Laboratories, LLCInventor: Todd Kaplan
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Patent number: 7002506Abstract: A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.Type: GrantFiled: December 23, 2004Date of Patent: February 21, 2006Assignee: Texas Instruments IncorporatedInventors: Preetam Charan Anand Tadeparthy, Jomy G Joy, Gaurav Chandra, Sumeet Mathur
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Patent number: 7002375Abstract: A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.Type: GrantFiled: March 31, 2003Date of Patent: February 21, 2006Assignee: Intel CorporationInventors: Steven K. Hsu, Ram Krishnamurthy, Chris Hyung-il Kim
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Patent number: 6999019Abstract: A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.Type: GrantFiled: April 8, 2004Date of Patent: February 14, 2006Assignee: The Boeing CompanyInventor: Albert E. Cosand
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Analog-to-digital converting circuit and image processing circuit cyclically repeating AD conversion
Patent number: 6995703Abstract: A first AD converting part of an AD converter converts an input voltage into a digital value of a predetermined number of bits and output the digital value to a digital output circuit and a DA converting part. The DA converting part converts the digital value into an analog value. A subtracting part outputs a difference between the analog value output from the DA converting part and the original input voltage. An amplifying part amplifies the difference output from the subtracting part. An output from the amplifying part is input to the first AD converting part via a feedback path. A subsequent output from the amplifying part is input to the second AD converting part via a branch path so as to produce a digital value of a predetermined number of bits. While the second AD converting part performs conversion, a subsequent input voltage is subjected in parallel to AD conversion by the first AD converting part.Type: GrantFiled: April 26, 2004Date of Patent: February 7, 2006Assignee: Sanyo Electric Co., Ltd.Inventor: Shigeto Kobayashi -
Patent number: 6995693Abstract: Several embodiments of a multiple input diversity decoding apparatus and method are disclosed. In one embodiment, two or more diversity decoders work together to iteratively decode information. Each diversity decoder can include two or more partial decoders. In another embodiment, a plurality of partial decoders work together to iteratively decode information received in a diversity application.Type: GrantFiled: December 4, 2003Date of Patent: February 7, 2006Assignee: Rockwell Collins, Inc.Inventor: Ray Lynn Cross
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Patent number: 6992506Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.Type: GrantFiled: April 1, 2004Date of Patent: January 31, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Min-sang Park, Jin-seok Kwak, Seong-jin Jang
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Patent number: 6992606Abstract: System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is configured to sum a difference between an input signal and an output of the sigma-delta modulator. A dithering circuit, also coupled to the signal input, is used to produce a dithering sequence. A summing point combines an output of the integrator and the dithering circuit while a quantizer converts the combined outputs into one of several discrete levels. The sigma-delta modulator further comprises a reset circuit to reset the sigma-delta modulator if the integrator becomes saturated. The sigma-delta modulator, as described, is compatible with G.Lite, ADSL, and ADSL+ variants of the digital subscriber line technical standards.Type: GrantFiled: June 10, 2004Date of Patent: January 31, 2006Assignee: Texas Instruments IncorporatedInventors: Thomas Nicholas Zogakis, Himamshu G. Khasnis, Baireddy Vijayavardhan