Abstract: An analog to digital conversion circuit includes a voltage-to-charge converter coupled to a charge integrator and a comparator. The voltage-to-charge converter is coupled to, and converts the voltage of, an analog signal or one of a set of reference voltages, into an equivalent charge. The charge integrator then adds or subtracts that equivalent charge in an iterative manner based on an output of the comparator. The initial charge of the charge integrator is based on a previous conversion. When plural analog to digital conversion circuits are used the initial charge in each such circuit may be different, as each initial charge serves to automatically compensate for any offset in the output of the circuit.

Abstract: The present invention relates to noise shaping, especially although not exclusively for digital audio signal processing; and in particular for PCM-PWM converters in a digital amplifier.

Abstract: A low power analog output circuit is disclosed that utilizes a low pass filter driven by a bit stream to render a waveshaped output signal based upon a raw digital data signal. The analog output circuit includes sequential bit pattern selection logic that receives as an input, the raw digital data signal. The analog output circuit also includes a bit pattern storage that specifies bit stream sequences that are selected in accordance with control signals generated by the state machine based upon its current state and the current raw digital data signal. The analog output circuit includes an output stage driven by a digital input signal corresponding to values provided by a bit stream sequence selected from the bit pattern storage. The output stage comprises a low pass filter circuit having an effective time constant that is greater than a hold period associated with a single bit of the bit stream sequence that drives the digital input signal.

Abstract: A data driving circuit and method for an organic light emitting diode display. Data lines transmit first digital data in a first cycle, and subsequent digital data in a second cycle. A D/A converter electrically connected to the data lines converts the first digital data to first analog data, and converts the subsequent digital data to second analog data. Each analog sampling storage circuit electrically coupled to the D/A converter, in the first cycle, stores the first analog data, in the second cycle, outputs the first analog data and stores the second analog data, and in a third cycle, outputs the second analog data.

Abstract: Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between magnitudes of first adjacent samples and interleaved second adjacent samples of the converters. The difference signals can be applied (e.g., to a converter's input sampler or to a variable delay element inserted after the converter) to substantially reduce the phase errors. The methods and controllers may be economically implemented because they can be realized with simple operations (e.g., addition and subtraction). Although some embodiments are facilitated with knowledge of parameters of the analog input signal, others do not require this knowledge so long as the signal is restricted to lie within a single Nyquist zone.

Abstract: In a process for data compression, data to be encoded is received. The received data is based on an alphabet including one or more symbols and coded bits are assigned to each symbol of the received data. In addition, the coded bits are based on a probability estimation using a variable probability estimation factor.

Abstract: Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output of the first logic gate, and has a gate terminal coupled to the first word line. The second pass gate is coupled between the bit line and a second storage node at the output of the second logic gate, and has a gate terminal coupled to the second word line. The bit line and one of the word lines can be used to selectively set or reset a given static memory cell, if desired, without affecting other memory cells along the word line. In some embodiments, the static memory cell is a configuration memory cell of a programmable logic device (PLD).

Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.

Abstract: One embodiment of the invention includes a system comprising an analog baseband signal input, a conversion circuit with N Analog to Digital Converters (ADCs) operable to receive the analog baseband signal, and a Finite Impulse Response (FIR) filter operable to receive outputs of the N ADCs and to produce a digital representation of the analog baseband signal corrected for a mismatch in the N ADCs.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: An analog-to-digital sigma-delta modulator for converting analog input signals to digital output signals comprises a feedback path (1, 101, 201) for producing analog feedback signals that are a function of the digital output signals (y, Y), an ‘N’-stage (‘N’=2) integrator path (9 to 14, 109 to 114) for integrating analog difference signals that are a difference function of the input signal and the analog feedback signals, and a quantizer (3, 103) responsive to the signals integrated by the integrator means (9 to 14, 109 to 114) for producing the digital output signals (y, Y) at clock intervals. The feedback path includes ‘N’ feedback stages (15 to 17, 115 to 117) for respective integrator stages (9 to 14, 109 to 114).

Abstract: Digital data is embedded in codes used to identify beginnings of regions of modulated data bit streams. Data may be designated by a choice of one code from a plurality of alternative codes, or data may be designated by a variable field within a code.

Abstract: There is provided a superconducting multi-stage sigma-delta modulator including a first superconducting sigma-delta modulator having a first integrator and a first comparator and outputting a sigma-delta modulated signal and a second superconducting sigma-delta modulator having a second integrator and a second comparator and outputting a sigma-delta modulated signal. The first integrator and the second integrator are magnetically coupled.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. Reducing power consumption of a SAR system can be readily accomplished by reducing comparator supply voltage. For a SAR converter architecture using a CAPDAC array or CAPDAC (capacitor array DAC), fairly large variations in comparator input voltage can be expected under these circumstances.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: A method and device for adding or extracting a secondary information signal to/from a runlength-limited code sequence, includes detecting a polarity of a runlength at a first predetermined position of the runlength-limited code sequence and setting a parameter reflecting the degree of freedom that is present in the runlength-limited channel code, e.g., the selection of a merging bit pattern in the CD-standard, on the basis of the detected polarity so as to obtain a predetermined polarity of a runlength at a subsequent second predetermined position of the runlength-limited code sequence. The predetermined polarity then corresponds to a binary value of the secondary information. Thus, a side-channel with a small capacity is provided, which is positioned very close to the physical channel such that the secondary information is hard to be detected from the EFM bit stream. Therefore, the side-channel can be used as a hidden channel for copy protection purposes.

Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.

Abstract: In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.