Abstract: A comparator is used as a microcontroller peripheral and is programmable for either high-speed or low-power operation. High-speed operation requires higher operating current than the operating current required in the low-power mode, but enables much faster response to changes in input signals. When in the low-power mode, the quiescent current of the comparator circuit is minimal but the response is slower to changing input signals. Current control is used on the first input stage, which affects the current consumption of the subsequent stages. The current consumption is adjusted by switching in and out different current sources for the differential input stage of the comparator.

Abstract: A rear-mount integrated rotary encoder comprises a mechanical portion and a printed circuit board portion. The mechanical portion of a rear mount integrated rotary encoder comprises a housing including a bushing for receiving one end of a rotatable. The rotatable shaft passes through an open front portion of the housing and is mechanically connected to exposed rotatable circuit contacting members. The printed circuit board portion has an encoder contact pattern formed thereon. The printed circuit board has an area larger than the cross sectional area of the housing. The encoder contact pattern surrounds an aperture in the circuit board. The rotatable shaft of the rotary encoder is passed through the aperture such that the rotatable circuit contacting members contact the encoder contact pattern on the circuit board. The housing includes projections, substantially orthogonal to the circuit board, for engaging a feature of the circuit board for securing the integrated encoder in an assembled state.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y1, y2, y3) in accordance with a conversion of the Jacoby type, where m and n are integers, with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.

Abstract: Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block.

Abstract: Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.

Abstract: The invention relates to compressing and decompressing digitized analogue signals, such as speech or music, by continuously adjusting the sampling rate to the time-varying information density of any given signal. The invention consists of three main parts: 1) a technique for measuring the time-varying information density of the signal, utilizing a line search for the optimal time-varying rate. 2) a technique for compressing and decompressing the signal by digitally resampling the signal from a constant high rate to a time-variable lower rate that follows the measured time-varying information density in the signal, and 3) a technique for decompression by resampling back to a constant high rate. The preferred embodiment utilizes a generalization of the cardinal series reconstruction kernel which is directly expressed in terms of the varying sampling rate.

Abstract: A superconductor filter includes a superconductor receiver filter of a planar transmission line structure including a signal input line, a resonator element and a signal output line and configured to select a signal received from an antenna, a superconductor transmitter filter of a planar transmission line structure including a signal input line, a resonator element and a signal output line and configured to select a signal transmitted to the antenna, the transmitter filter being arranged non-parallel to the receiver filter, and a heat-insulating container housing the superconductor receiver filter and the superconductor transmitter filter.

Abstract: Two LC resonance circuits, each including a parallel combination of an inductor and a capacitor and both magnetically coupled, are connected between an input terminal and an output terminal, and a parallel resonance trap circuit including a parallel combination of an inductor and a capacitor is connected in series between at least either the input terminal, the output terminal and the LC resonance circuit.

Abstract: A system and method for simultaneously and synchronously encoding a data signal in multiple formats and at multiple bit rates. According to one aspect of the invention, plural encoding stations are controlled by one central controller, which controls the encoding format carried out by each encoding station, and also controls the commencement of the encoding process to ensure that each encoding station simultaneously commences the encoding process, thereby synchronizing the encoded streams.

Abstract: A programmable logic device (PLD) can be configured using configuration data stored on a memory. The configuration data is compressed using a compression algorithm before being stored on the memory. When the PLD is to be configured, the compressed configuration data is read from the memory, decompressed, then loaded onto the PLD.

Abstract: Automatic slice level control response to differential input signals is provided to remove in-phase noise and effects on S/N ratio Analog differential input signals Vinp and Vinn are inverted with respect to each other and applied to input terminals in1 and in2 of a comparator via resistors R1 and R2. A data stream is provided giving DSV=0. A charge pump is driven by a digital signal from the comparator. A transconductance amplifier produces output current Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump and a reference voltage Vref. The output currents are supplied to the input terminals in1 and in2 of the comparator to provide a DSV=0.

Abstract: The systems and methods relate to the compression of multiple files into a single file called an archive. Before appending the multiple files as one file to be compressed, the systems and methods arrange the order of files to increase the potential of redundancy among neighboring files, thus providing potential improvement in compression ratio and compression speed. In using a dictionary method to compress the multiple files appended as one file, a large dictionary is used in one embodiment to take advantage of potential between-file redundancies. In another embodiment, the redundancy characteristics of the multiple files are examined to dynamically determine the dictionary size. After the dictionary compression method produces an intermediary output data file, the intermediary output data may be separated into multiple sections, and a compression method that is potentially suitable for the data characteristics of each section may be applied.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.

Abstract: A signal processing apparatus having: a plurality of circuit blocks each circuit block including a signal source and an output transistor adapted to receive a signal generated by the signal source at a control electrode region and output a corresponding signal from a main electrode region; and an analog/digital converter circuit adapted to sequentially process the signal from each of the plurality of circuit blocks, wherein the analog/digital converter circuit includes a reference transistor for receiving a reference level at a control electrode region and outputting a corresponding signal from a main electrode region and a digital output circuit for outputting a digital signal in accordance with a signal output from the output transistor and a signal output from the reference transistor, and wherein the output transistor and reference transistor constitute an input unit of a differential amplifier circuit including the output transistor and reference transistor.

Abstract: A pole-shifted noise shaper whose transfer function has a Z-plane in which the pole has been shifted out of the origin. The noise shaper suppresses idle pattern. The noise shaper has a dither adder (17) placed immediately before a quantizer (16) to add a dither signal to data about to be applied to the quantizer (16). This suppresses attenuation of the dither signal due to noise shaping. Therefore, the dither signal can be supplied effectively. The idle pattern appearing in the output signal can be suppressed. Since the pattern of the dither signal is varied at a frequency that is {fraction (1/16)} to ⅛ of the frequency of the operating clock signal, the frequency of noise component due to the dither signal lowers. The signal and the dither signal component can be easily separated in a rear stage.

Abstract: A microswitch is realized that can be driven by low voltage, and at the same time, that has increased impedance between switch terminals when the switch is OFF. The relation between upper electrode (4), lower electrode (6), contact electrode (7), and signal lines (8) is arranged such that the minimum distance between contact electrode 7 and signal lines 8 is greater than the minimum distance between upper electrode 4 and lower electrode 6 when the microswitch is in the OFF state.

Abstract: A method of VCODAC adjustment of speed is disclosed. Values of a VCO digital/analog converter (VCODAC) generator according to the frequency of every speed are estimated at first, and then an output of a loop filter is used to on-line adjust the value to an optimum value. As the pick up head reads the same position, it need not be adjusted again. The reading ability of an optical disk drive is improved.

Abstract: A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data stream, which consists of the binary data to be coded, into data blocks having a predetermined data block length, a calculating device for calculating the difference between the number of binary data having a second binary state, for each data block, and a transmitting device for transmitting each data block as transformed data block or as non-transformed data block via a communication channel connected to the transmitting device, in such a manner that the total sequence of the data blocks transmitted by the transmitting device on the communication channel exhibits the particular transmit signal spectrum.

Abstract: An apparatus that has a feedback circuit that couples a wireless receive channel to a frequency synthesizer. A method that reduces an offset in a baseband signal by changing a downconversion frequency in response to the offset.