Patents Examined by Patrick Wamsley
  • Patent number: 6642873
    Abstract: A Multi-level digital-to-analog (D/A) converter is incorporated with a multi-level quantizer in a multi-bit sigma-delta analog-to-digital (A/D) converter. The multi-level D/A converter is realized by feeding back reference voltages of the multi-level quantizer through a switch. The summation of electrical energy from multiple D/A converter elements found in conventional D/A converters is avoided so that element mismatch and circuit complexity are reduced significantly in the multi-bit sigma-delta A/D converter.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: November 4, 2003
    Inventor: Wensheng Vincent Kuang
  • Patent number: 6639535
    Abstract: A digital-analog converter for producing less distorted output waveforms without the need for an increase in the operating speed of components. A D/A converter 1 comprises a memory 10, an address counter 12, a B spline function generation circuit 14, four sampling function generation circuits 16, three delay circuits 18, four amplifiers 20, and three adding circuits 22, 24 and 26. Four items of digital data supplied one after another in the predetermined time interval T are stored in the memory 10. The gain of each of the four amplifiers 20 is set according to the corresponding digital data. The four sampling function generation circuits 16 generate signal waveforms of the sampling function, which appear individually in points a time T away from one another. The signal waveforms are amplified in the amplifier 20 and added to produce an analog signal associated with the interpolation value.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: October 28, 2003
    Assignee: Niigata Seimitsu Co.., Ltd.
    Inventors: Kazuo Toraichi, Kouichi Wada
  • Patent number: 6633247
    Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: October 14, 2003
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventor: Masami Yakabe
  • Patent number: 6633244
    Abstract: A system and method for lossless data compression. A mathematical transform equivalent to the content value of the data, and taking fewer bits to represent, is found.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 14, 2003
    Assignee: Efeckta Technologies Corporation
    Inventors: Caleb Avery, Ralph Tobelmann
  • Patent number: 6628224
    Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: September 30, 2003
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Christopher Michael Ward
  • Patent number: 6628216
    Abstract: A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 30, 2003
    Assignee: Intersil Americas Inc.
    Inventors: Hsin-Shu Chen, Kantilal Bacrania, Eric C. Sung, J. Mikko Hakkarainen, Bang-Sup Song, Brian L. Allen, Mario Sanchez
  • Patent number: 6624773
    Abstract: A scrambling or encryption method involves analog-to-digital, digital-to-analog, analog-to-analog or digital-to-digital conversions that are constructed from one or more analog-to-digital or digital-to-analog conversions. For example, encryption of an analog signal converts the analog signal to an intermediate digital signal that is converted back into a scrambled analog signal. Encryption of a digital signal converts the digital signal to an intermediate analog signal that is converted back into an encrypted digital signal. The conversions between analog form and digital form and back can be repeated. A codec scrambling/descrambling and encryption/decryption implements one or more different analog-to-digital conversions and one or more digital-to-analog conversions. One embodiment of the codec includes a programmable conversion array that includes an array of transistors such as floating gate transistors in memory cells.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 23, 2003
    Assignee: SanDisk Corporation
    Inventor: Sau C. Wong
  • Patent number: 6624762
    Abstract: The present invention is directed to an improved system for creating LZW compressed files by executing the LZW data compression algorithm on a plurality of special-purposed pipelined processing units, each of which contains hardware-embedded control algorithms. The data paths of the plurality of processors, together with the state machines that control the flow of data through them, provide pipelined execution of the LZW algorithm. For example, at the same instant, processor three can be processing a first input byte, processor two can be processing a second input byte, and processor one can be processing a third input byte.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: September 23, 2003
    Assignee: Unisys Corporation
    Inventor: Joseph H End, III
  • Patent number: 6624777
    Abstract: For the proper delivery of digital data D_AD from a fast A/D converter to a digital signal process section, the digital data is stored in a dual-clock-synchronous FIFO by being timed to the output of digital data from the fast A/D converter (at the timing based on a data ready signal DATA_RDY). The dual-clock-synchronous FIFO reads out digital data D_FIFO and delivers to the digital signal process section by being timed to the operation of the digital signal process section (at the timing based on a clock signal CLK_DIG for a digital signal process).
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: September 23, 2003
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventor: Hiroyuki Miyano
  • Patent number: 6624778
    Abstract: A plurality of amplifying circuits having generally uniform amplifying and impedance characteristics, a reference voltage network applying reference voltages of a generally uniformly spacing to each reference voltage terminal of said amplifying circuits, wherein a relative functional position of each amplifying circuit is determined by the magnitude of a received reference voltage; an averaging network, comprising of generally identical averaging impedances coupling output voltage terminals of adjacent amplifying circuits; wherein the amplifying and/or impedance characteristics of said termination circuit and/or the termination reference voltage, and/or the termination averaging impedance are deviant to generate a current in said output voltage terminal of said outer amplifying circuit of said array, that is corrected for the finite size of the array.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 23, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Peter Cornelis Simeon Scholtens
  • Patent number: 6624761
    Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: September 23, 2003
    Assignee: Realtime Data, LLC
    Inventor: James J. Fallon
  • Patent number: 6621376
    Abstract: An impedance-matching circuit for a multiband power amplifier, which uses an impedance-matching circuit with one-to-multiple path to efficiently transmit a radio frequency (RF) from an input port to the corresponding multi-ports without spurious effect. The impedance-matching circuit includes an input port for receiving a plurality of frequency band signals; a plurality of output ports for outputting the plurality of frequency band signals; and a plurality of frequency paths in which each path has an impedance matching network for matching an input port's impedance with its output port's impedance in a desired band; and a short circuit for filtering out RF signals in other remaining bands.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: September 16, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Ping Liu, Yung-Nien Chiu, Tseng-Chuan Wang
  • Patent number: 6614369
    Abstract: The present invention provides techniques for classifying disparities and source vectors for 7B/8B and 9B/10B transmission codes, which are then used to minimize the complexity of decoding and encoding for 16B/18B codes. The classifications are determined for source vectors and for disparity for coded vectors. The vector classifications are selected in a predetermined manner so that the number of classifications is minimized for bit mapping, disparity control, or both. Additionally, the number of bits changed for bit mapping is minimized. Decoding of 7B/8B and 9B/10B transmission codes is performed by converting coded vectors into a single image and then performing decoding operations to decode the single image of the coded vectors. The single image is a primary coded vector, and an alternate coded vector is an inverted version of the primary coded vector. Techniques are presented for using 5B/6B, 7B/8B and 9B/10B transmission codes in other transmission codes such as 12B/14B and 17B/20B transmission codes.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: September 2, 2003
    Assignee: International Business Machines Corporation
    Inventor: Albert X. Widmer
  • Patent number: 6611218
    Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: August 26, 2003
    Assignee: Xilinx, Inc.
    Inventors: Jinghui Lu, Michael A. Nix
  • Patent number: 6600438
    Abstract: Correction of differences between two analog to digital converters (ADCs) in broadband intermediate frequency conversion. By stimulating a two-ADC system with a known input, the impulse response of the system is derived, and from that impulse response a finite impulse response filter is derived which corrects for mismatches between the ADCs.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: July 29, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Howard E. Hilton
  • Patent number: 6600437
    Abstract: A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: July 29, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Pierangelo Confalonieri, Marco Zamprogno, Angelo Nagari
  • Patent number: 6597258
    Abstract: A high performance diplexer is disclosed having a common conductor which branches into two resonators in distributive form. The diplexer may be used reciprocally, has low insertion loss, is tuneable, has high signal isolation and impedance matching, and may be readily produced to meet the space requirements relating to size, temperature, radiation and performance. A method of tuning the resonators of the diplexer is also disclosed. Specific applications for the diplexer are also disclosed and include use in a GPS transmitter, GPS receiver and as part of an electronic scan array (ESA) antenna. The diplexer's small size and weight, and its resistance to the conditions of space make it ideal for use in satellite applications.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 22, 2003
    Assignee: Spectrum Astro
    Inventor: Glen Var Rosenbaum
  • Patent number: 6587057
    Abstract: A fast, memory efficient, lookup table-based system for VLC decoding. Code words are grouped by prefix and recoded to reduce the number of bits that must be matched, thus reducing the memory requirements. General-purpose processor and finite state machine decoder implementations are described.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: July 1, 2003
    Assignee: QuickSilver Technology, Inc.
    Inventor: W. James Scheuermann
  • Patent number: 6583747
    Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: June 24, 2003
    Assignee: Broadcom Corporation
    Inventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
  • Patent number: 6573802
    Abstract: A single-ended to differential converter including a common mode shunt and a load element. The common mode shunt includes first and second reactive elements each having first ends coupled together at a common mode junction. The second end of the first reactive element receives a single-ended input signal referenced to a reference signal, such as ground. The common mode shunt further includes a third reactive element coupled between the common mode junction and ground. The load element is coupled between the second end of the second reactive element and ground. A single-ended input signal is applied at a second end of the first reactive element and the differential signal is developed by the first and second reactive elements. The common mode shunt serves as a differential to single-ended converter by applying the differential signal as an input in which a single-ended output signal develops at the load element.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: June 3, 2003
    Assignee: Intersil Americas Inc.
    Inventor: A. Michael Straub