Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: The invention provides a dielectric filter device having first bore opening portions arranged between a first electrode formed on an upper surface or side surface of a dielectric block and a second electrode formed on the upper surface to provide a filter for passing a predetermined frequency band, and a second bore opening portion disposed between the second electrode and the side surface of the block. A conductive layer on the outer peripheral side surface close to the second electrode is removed in the form of a strip from at least one portion of the peripheral side surface which portion extends from the upper surface to the lower surface of the block. Unnecessary resonance in a high frequency range outside the pass band can be suppressed without providing an external circuit.

Abstract: An arithmetic coding apparatus for carrying out complete pipeline processing is provided. This arithmetic coding apparatus analyzes an input image, reads image information accurately and performs arithmetic coding at ultra-high speed. Using a future prediction type Qe memory removes disturbance in the pipeline caused by renormalization. The arithmetic coding apparatus also generates a common context when coding multi-valued images without distinguishing between an AC component and DC component of a DCT coefficient. The apparatus is also provided with a circuit for outputting an arithmetic code which is a variable-length code with the length fixed to facilitate editing of a reconstructed image.

Abstract: A method and apparatus are provided for calibrating first and second digital-to-analog converters (DACs). The apparatus has a normal input and a test input. A first correction circuit selectively modifies either the normal input or the test input by a first gain correction value and a first offset correction value to produce a first corrected value. A second correction circuit selectively modifies either the normal input or the test input by a second gain correction value and a second offset correction value to produce a second corrected value. A first DAC operates on the first corrected output and has a first analog output. A second DAC operates on the second corrected output and has a second analog output. A calibration control circuit has first and second inputs coupled to the first and second analog outputs, respectively, and generates the first and second gain correction values and the first and second offset correction values as a function of the first and second analog outputs.

Abstract: In a method for position coding, positions are coded in a first dimension on a surface in accordance with a primary number sequence that has the property that the place in the primary number sequence of each partial sequence of a first predetermined length is unambiguously determined. Each position in the first dimension is coded by one of the partial sequences. The primary number sequence is built up of at least two secondary number sequences that have a smaller base than the base of the primary number sequence and that are used for determination of the partial sequences of the primary number sequence which correspond to the positions in the first dimension. This makes possible, among other things, realization of the method in devices with limited memory capacity, as the secondary number sequences require less memory in total than the primary number sequence. The secondary number sequences can also be used for decoding the position code.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y1, y2, y3) in accordance with a conversion of the Jacoby type, where m and n are integers, with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: An optical analogue to digital (A/D) converter for converting an input analogue voltage signal into a digital output, comprising means for frequency modulating an optical signal with an input analogue voltage signal, delay means for splitting the frequency modulated optical signal and generating at least one differentially delayed signal and at least one reference signal, at least one combining means arranged to combine the or one of the delayed optical signals with the or one of the reference signals, and at least one converter means for converting a combined signal output from an associated one of the combining means to a digital code.

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type comprising at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUT1) through at least one integrative/proportional branch (120, 121, 130, 134). Advantageously in this invention, the analog-to-digital converter (100, 100*) is an integration converter adapted to integrate the error signal (Error) before an analog-to-digital conversion thereof.

Abstract: The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A2) with quantization at N levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A2) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A2) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter (24) using said correction values.

Abstract: An analog-to-digital converting includes a fanned out module for receiving an input signal and producing a plurality of new signals. A plurality of analog to digital converter modules receive the new signals from the fanned out module. Each of the new signals is assigned at least one of the analog to digital converters, such that the digital converter modules produce a plurality of digitized signals from each of their associated new signals. A combiner module receives the plurality of digitized signals, and combines the plurality of digitized signals to form a single digitized signal.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.

Abstract: A switching signal generator for a switching power supply employing a DC-DC modulator has an adder, an integrator and a quantizer. A gate driver circuit is provided upstream of a power switch element and receives a quantizer output. By feeding back a gate driver circuit output to the adder of the &Dgr;&Sgr;-modulator, a large phase margin is obtained at a high-frequency switching. The switching signal generator for the &Dgr;&Sgr;-modulation type switching power supply has an improved direct-current transmission linearity characteristic relative to direct-current input, and that is stably controllable and of high efficiency. Furthermore, a DC-DC converter has an adder, an integrator and a quantizer, the integrator having a mechanism for adjusting its gain.

Abstract: Quadrature sampling architecture and method are disclosed for analog-to-digital converters that provide improved digital output signals over prior quadrature mixing implementations. Sampling circuitry according to the present invention samples an input signal with a first and second sampling signals to produce real and imaginary sampled output signals. The first sampling signal, which is associated with the real sampled output signal, is delayed by one-fourth cycle with respect to the second sampling signal, which is associated with the imaginary sampled output signal. This one-fourth cycle sampling signal difference allows for simplified construction of the sampling circuitry. In addition, filter circuitry according to the present invention processes the real and imaginary digital data output signals so that the imaginary digital data output signal is advanced by one-fourth cycle with respect to the real digital data output signal.

Abstract: A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.

Abstract: A code word generator for OVSF codes, comprising an intermediate memory device (16) which is used to input a calculation index as a binary calculation index data word, a calculation device (17) which permutes the significant data bits of the calculation index data word bit-by-bit so that a calculation basis (B) can be generated, a counter (21) for producing a counting variable (Z) and provided with a logic circuit comprising several AND gates for bit-by-bit linkage of the counting variables (Z) generated with the calculation basis (B) in order to form a linking data word and several XOR gates for logical reduction of the linking data word to form code word data bits of the OVSF code word.

Abstract: In order to accommodate increasing operation speed of a digital circuit, a distributed constant type noise filter having a low impedance transmission line optimal to provide a power de-coupling of an LSI operating at high speed is provided. Particularly, a capacitor-forming portion of the distributed constant type noise filter is constructed with a solid electrolytic capacitor having a 3-terminal structure. In the distributed constant type noise filter constructed as mentioned, a ratio of width W of the capacitor-forming portion to thickness d of a dielectric member thereof and length L of the capacitor-forming portion are set on the basis of dielectric constant of the capacitor-forming portion such that electric noise generated by an electron device connected thereto are removed over a wide frequency range thereof.

Abstract: Data is compressed through implementing the inserting of a regressive reference string scheme, each such reference replacing a particular data string through referring to an associated earlier data string of identical content. In particular, the regressive string reference item to an encoded object is inserted as being based on pointing and delimiting a pointee string, and identifying the reference item through an associated signalling element.

Abstract: A small high frequency circuit component has very small variations in stray capacitance generated between an inductor electrode pattern and a capacitor electrode pattern. As a result, the variations in the characteristics thereof are also small. The inductor electrode pattern is overlaid with the capacitor electrode pattern in a plan view. That is, when viewed from the lamination direction, the projection of the inductor electrode pattern onto the capacitor electrode pattern is included within the capacitor electrode pattern. More particularly, outer dimensions W1, L1, D1 of the inductor electrode pattern and corresponding outer dimensions W2, L2, D2 of the capacitor electrode pattern satisfy the following conditions, respectively: W2=W1+&Dgr;, where 0.1 mm≦&Dgr;≦1.0 mm, L2=L1+&Dgr;, where 0.1 mm≦&Dgr;≦1.0 mm, and D2=D1+&Dgr;, where 0.1 mm≦&Dgr;≦1.0 mm.