Abstract: A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

Abstract: An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which selects a voltage based on a selection signal and feeds the reference voltage to a conversion device of the converter. A correction network is provided for correcting offset and linearity errors. The plurality of reference voltages are freely selectable reference voltages, and the specific reference voltage defining the conversion is freely selectable, that is, it is freely selectable what reference voltage is used to carry out a respective conversion.

Abstract: A waveguide structure that has two rotating parts changes the polarization of a radio frequency signal in two steps or one step. The waveguide structure includes input and output waveguides and a polarization rotator. The output waveguide includes two cavities corresponding to two polarizations. The rotator includes cut-away portions of a rectangular shape which are rotated with respect to each other and the first wave guide by predetermined angles. When the second waveguide is rotated from one cavity to another, the rotator is also rotated, thereby changing the polarization of the signals passing through the waveguide. In addition, if the rotator and the second waveguide are interlocked, then the number of steps required to accomplish the polarization change can be reduced to one, because rotation of the second waveguide will cause the rotation of the polarization rotator.

Abstract: A vehicular audio system receives audio inputs from audio sources and a radio receiver. Analog audio is converted to digital, and digital audio remains natural digital. The receiver front end converts a radio signal to an intermediate frequency then an ADC converts that to a digital signal. The inputs that are converted to digital are selectively mixed with each other and with the natural digital signals. This allows for sounds from multiple sources to be heard simultaneously so that a telephone ring may be provided without requiring background music to be interrupted and for uses such as voice by microphone over a music tape. A reference frequency to the receiver front end of 7.2 MHz is particularly beneficial for noise reduction and consequent mixing of digital audio at 48 KHz, the standard frequency for typical digital audio inputs.

Abstract: A waveguide type duplex filter having first and second waveguides which each comprise filtering means tuned to a given frequency, comprises two halves having a conducting surface. Faces directed toward each other are formed with channels which, when the halves have been assembled, constitute said waveguides. The filtering means are produced by means of a sheet having a conducting surface arranged between the two halves, and the conducting surface has openings which define and delimit resonators in the waveguides. The sheet can be arranged in first and second positions. In the first position, the resonators in the first waveguide are tuned to a first frequency, while the resonators in the second waveguide are tuned to a second frequency. In the second position, the resonators in the first waveguide are tuned to the second frequency, while the resonators in the second waveguide are tuned to the first frequency.

Abstract: Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats. The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats.

Abstract: A microcomputer for performing an inverter control includes three AD converters provided therein. The first and second AD converters are used for a motor control, and each receive a motor position detection signal. The third AD converter is used for a power supply control, and receives an analog signal representing the state of the power supply. Therefore, a motor control and a power supply control are performed by using separate AD converters, whereby it is possible to optimally perform each control without an AD conversion having to wait for another AD conversion to be completed.

Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.

Abstract: There is provided an A/D converter circuit capable of high-speed operation without fluctuation of reference voltage due to comparison operation by high-order comparators influencing voltage level of reference voltage of voltage comparison by low-order comparators. First switches SW11A, SW12A, and SW13A and second switches SW11B, SW12B, and SW13B are arranged between reference voltage terminals (REF) of high-order comparators COMP 11, 12, and 13 and voltage-divided terminals (N1), (N2), and (N3) of ladder-resistance-element array, respectively. Voltage holding capacitance elements C11, C12, and C13 are connected to connection points between the first switches SW11A, SW12A, and SW13A and the second switches SW11B, SW12B, and SW13B. When input voltage VAIN is fetched, the first switches SW11A, SW12A, and SW13A are turned on so as to fetch high-order reference voltage VN1, VN2, and VN3 to the voltage holding capacitance elements C11, C12, and C13.

Abstract: A high performance diplexer is disclosed having a common conductor which branches into two resonators in distributive form. The diplexer may be used reciprocally, has low insertion loss, is tuneable, has high signal isolation and impedance matching, and may be readily produced to meet the space requirements relating to size, temperature, radiation and performance. A method of tuning the resonators of the diplexer is also disclosed. Specific applications for the diplexer are also disclosed and include use in a GPS transmitter, GPS receiver and as part of an electronic scan array (ESA) antenna. The diplexer's small size and weight, and its resistance to the conditions of space make it ideal for use in satellite applications.

Abstract: A microstrip-to-waveguide power combiner includes a dielectric substrate and at least two microstrip transmission lines formed thereon in which radio frequency signals are transmitted. The microstrip transmission lines terminate in microstrip launchers or probes at a microstrip-to-waveguide transition. A waveguide opening is positioned at the transition. A waveguide back-short is positioned opposite the waveguide opening at the transition. Isolation vias are formed within the dielectric substrate and around the transition and isolate the transition. A coaxial-to-waveguide power combiner is also disclosed.

Abstract: A feed-forward dc-offset canceller, for use in direct conversion receiver (DCR) architecture wireless systems, in which dc-offset is estimated from the down-converted signal at the mixer output, and the offset is cancelled before applying the signal to the analog baseband section. A linear digital filter estimates and tracks the dc-offset, which is subtracted from the down-converted signal before the analog baseband input. The response of the filter can be adjusted by its coefficients according to different environments and standard requirements. Although higher order filters can be used depending on the requirements, preferably, a first order recursive filter is used as it has the advantages of being a very simple and efficient structure.

Abstract: A plurality of composite elements are arranged in parallel with each other on a substrate. The composite elements each include a rectangular microstrip line element, an input microstrip line and an output microstrip line. The microstrip line element has one longer side, the other longer side, one end and the other end, and the input microstrip line is connected at the one end to the one longer side while the output microstrip line is connected at the other end to the other longer side. The composite elements are cascaded to constitute a low-pass filter.

Abstract: An A/D converter includes first to Nth stages of A/D conversion units, which are connected in series, each A/D conversion unit converting an analog input signal into a digital output signal. Each of the A/D conversion units includes a) a sample-and-hold circuit, which holds an analog input signal; b) a selector which selects one from a plurality of reference voltage signals in accordance with a digital output signal outputted from the one stage preceding A/D conversion unit; and c) a comparator which compares an output signal supplied from the sample-and-hold circuit with the reference voltage signal selected by the selector.

Abstract: The invention provides a dielectric filter device comprising a first electrode formed on a dielectric block for connection to an antenna, and a second electrode formed on an upper surface of the block for connection to a communications device, openings of hollow bores being arranged between the first and second electrodes to provide a filter for passing a predetermined frequency band, a plurality of hollow bores being arranged between the second electrode and a side surface of the block to provide traps having a plurality of attenuation poles. Attenuation of frequencies in the pass band can be diminished without providing an external circuit.

Abstract: The invention relates to a method of variable length coding in which data symbols are arranged into a number of sets, each of which comprises at least a first data symbol. At least two sets of variable length codewords are provided for variable length coding the data symbols and the sets of data symbols are variable length coded in a coding sequence, starting from a first set and progressing to a last set of data symbols. For a given set of data symbols, other than the first set of data symbols in the coding sequence, a set of cumulative information measures is determined, each of which is representative of a total amount of information required to variable length code the first data symbols of all the sets of data symbols preceding the given set of data symbols in the coding sequence using a predetermined one of the at least two sets of variable length codewords.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: A device having a capacitor for changing the impedance of a section of a coplanar waveguide is provided, the capacitance of the capacitor being changeable, the signal line of the section of the waveguide being interrupted for a predefined length, a first connection connecting the ground lines of the waveguide, and the second connection connecting both parts of the interrupted signal line.

Abstract: A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.