Abstract: A microcomputer for performing an inverter control includes three AD converters provided therein. The first and second AD converters are used for a motor control, and each receive a motor position detection signal. The third AD converter is used for a power supply control, and receives an analog signal representing the state of the power supply. Therefore, a motor control and a power supply control are performed by using separate AD converters, whereby it is possible to optimally perform each control without an AD conversion having to wait for another AD conversion to be completed.

Abstract: A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

Abstract: A wiring board includes a signal transmission circuit designed as a distributed constant circuit. The signal transmission circuit includes a first transmission line connecting a first electric component and a second electric component, and a second transmission line connecting the second electric component to a terminator resistor of the distributed constant circuit. At least the first transmission line includes a plurality of signal lines arranged in parallel, which transmit a signal in parallel.

Abstract: A data transmission system for interconnecting semiconductor integrated circuit devices, and a semiconductor integrated circuit adapted to the data transmission system are disclosed. The semiconductor integrated circuit has an input circuit, an internal circuit, and an output circuit. The input circuit has an ADC for converting a multi-value current data input from the outside to a collection of binary voltage level data. The internal circuit receives the collection of binary voltage level data from the ADC, and outputs the collection of binary voltage level data. The output circuit has a DAC for converting the collection of binary voltage level data output from the internal circuit to multi-value current data to output the multi-value current data to the outside.

Abstract: A method of analog encoder initialization involves repeatedly adjusting an encoder light element energization level and dc offsets of the encoder channels to produce desired signals.

Abstract: Self-calibration methods and structures are provided for pipelined ADCs which can be realized without requiring external measuring instruments or calibrators, without requiring major changes in pipeline structure and which can be rapidly obtained with stored calibration processes. In method embodiments, each of selected converter stages are calibrated by using succeeding stages as sub-ADCs which measure gain error at a transition step in a selected stage's residue transfer characteristic and saves the gain error as a calibration constant Ccal for that stage. After a first calibration constant Ccal has been obtained, the process is successively repeated for preceding converter stages except that previously-obtained calibration constants are multiplied by their respective stage's digital input signals Din to obtain weighted calibration constants Ccalwtd which are included in measured gain errors to thereby obtain preceding calibration constants Ccal.

Abstract: According to one embodiment, a method for programming a programmable logic device (PLD) may include reading configuration data from a memory device to program a first portion of a PLD to function as a data decompression circuit (304, 308). Compressed configuration data may then be read and decompressed by the first portion and used to program a second portion (310, 312, 315) with a user determined function. A first portion may then be reprogrammed with a user determined function (320, 324).

Abstract: A program for decoding variable-length codes like Huffman codes is generated by receiving information describing a particular coding scheme that defines an association between source symbols and the variable-length codes, generating a binary tree that represents the coding scheme, generating a lookup table from the binary tree that can be used to decode variable-length codes having a length less than or equal to a threshold length, and processing the binary tree and the lookup table to generate the decode program.

Abstract: A symbol string detection unit detects the second symbol string matching the first symbol string having a predetermined length n from input character strings. A matching length detection unit detects a matching length k between the third symbol string following the first symbol string and the fourth symbol string following the second symbol string. A coding unit codes an input symbol string based on the symbol string detected by the symbol string detection unit and the matching length k detected by the matching length detection unit.

Abstract: The invention provides a circuit arrangement for conversion of an input current signal (11) to a digital output signal (43). In particular, the invention relates to a method for providing a low-capacitance voltage node for a comparator input of a tracking analog/digital converter. An input circuit node (12a) is supplied with an input current signal (11). A feedback current signal (13) is produced by the input circuit node (12a) in order to operate a tracking analog/digital converter. A difference current signal (14) is likewise produced by the input circuit node (12a), and is supplied to a transimpedance resistance element (15) connected to the input circuit node. A second connection of the transimpedance resistance element (15) is connected to a reference circuit node (12b). An intermediate variable (22) is produced at the reference circuit node (12b), and is supplied to a downstream converter device (23). A constant voltage with respect to ground (33) is maintained at the input circuit node (12a).

Abstract: A method and apparatus for coding and decoding information are disclosed. The method is for encoding a message that includes a first set of binary digits. Each binary digit has a first value (“0”) or a second value (“1”). The method includes receiving a first set of binary digits, generating a second set of binary digits in response to the first set of binary digits (Y), and selecting the values of binary digits in the second set such that the number of binary digits having the first binary value in the second set is higher than the number of binary digits having the first binary value in the first set.

Abstract: A composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.

Abstract: An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero.

Abstract: A method and apparatus to convert geographic information to a binary representation, or bingeo. The geographic information can be converted to a bingeo for a selected reference or coordinate system, and with respect to a reference within the selected coordinate system. The coordinate system location to bingeo conversion can be hierarchical or iterative and can include segmenting the coordinate system or segments thereof. The iterative algorithm can include identifying a segment including the specified location, and segmenting the identified segment. During an iteration, segments can be assigned a binary code that can be incorporated into the bingeo. Successive segmentation iterations can be performed to provide increased precision. In one embodiment, a precision of 0.16 inches squared can be attained. Two bingeos can be compared, in the simplest form, using a bitwise logical XOR.

Abstract: The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.

Abstract: A symbol string detection unit detects the second symbol string matching the first symbol string having a predetermined length n from input character strings. A matching length detection unit detects a matching length k between the third symbol string following the first symbol string and the fourth symbol string following the second symbol string. A coding unit codes an input symbol string based on the symbol string detected by the symbol string detection unit and the matching length k detected by the matching length detection unit.

Abstract: An electronic system (10) is formed to include a circuit (11) having a digital-to-analog converter (12). Digital-to-analog converter (12) is formed to add an error voltage to the digital-to-analog converter output to adjust or translate the analog output value to include a power return offset value.

Abstract: A timing apparatus comprises a gear, for example a camshaft gear, and a timing ring secured to one side of the gear. The timing ring has a number of equally spaced timing teeth which when used with a sensor provide information about the rotation of the gear. The gear has a generally cylindrical recess on one face of the gear, and the timing ring is secured within the recess. The timing teeth are arranged radially inwardly of the gear teeth, so that the timing teeth are protected from damage. The resulting timing apparatus is economic to manufacture and facilitates compact adaption to a rotating body of an engine.

Abstract: A tuning circuit has a simple circuit construction and is capable of setting Q thereof to a high desired value. The tuning circuit is formed by a resonance circuit consisting of an inductor and a capacitor and a negative resistance circuit connected in series to the resonance circuit including a negative impedance converter and a variable resistor. A counter counts clock signals from a clock signal generating circuit and a count value is converted to an analog signal by a D/A converter. The negative resistance circuit is controlled by the analog signal so that an effective resistance of the tuning circuit is made negative to oscillate and to vary a negative resistance value in a positive direction. When the effective resistance value becomes zero, oscillation stops and thereafter when a value of Q becomes a predetermined value, the clock signals are stopped and the latch circuit holds a final count value.

Abstract: An analog to digital conversion (A/D) system produces a corrected output of an analog to digital (A/D) converter using at least one past signal sample. For example, the A/D system estimates a reference value or point, such as a reference amplitude, for the at least one past sample. In response to an indication that the A/D converter is saturated, the A/D system uses the reference value to predict a next reference value, such as a next amplitude value, from which a corrected digital sample value is produced to replace the saturating sample.