Abstract: An electronic package is provided and includes at least one electronic element, at least one first conductive structure and a second conductive structure disposed on one side of a carrier structure with at least one circuit layer, and an encapsulation layer covering the electronic element, the first conductive structure and the second conductive structure, where the first conductive structure is exposed from the encapsulation layer to externally connect required elements according to functional requirements.

Abstract: An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.

Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

Abstract: An image sensor includes pixel electrodes, a control electrode, a photoelectric conversion film arranged on the pixel electrodes, a transparent electrode arranged on the photoelectric conversion film, an insulating layer arranged on at least a portion of a top surface of the transparent electrode, and a connection layer that electrically connects the control electrode to the transparent electrode. The connection layer is in contact with at least one side surface of the transparent electrode. A side surface of the insulating layer, the at least one side surface of the transparent electrode, and a side surface of the photoelectric conversion film are aligned with each other.

Abstract: Provided is a semiconductor device enabling the flatness of a glass substrate to be maintained and enabling the end portion of the glass substrate to be sufficiently protected. A semiconductor device according to the present disclosure includes a glass substrate that includes a first surface, a second surface provided on the opposite side of the first surface, and a first side surface provided between the first surface and the second surface, a wiring that is provided on the first and second surfaces, a metal film that covers the first side surface, and a frame that is provided further on the outer side than the metal film, and that is bonded to the metal film at the first side surface.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

Abstract: A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Abstract: A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

Abstract: A semiconductor package. In some embodiments, the package has a top surface and a bottom surface, and includes: a semiconductor die having a front surface, a back surface, and a plurality of edges; a mold compound, on the back surface of the die and the edges of the die; a plurality of first conductive elements extending through the mold compound on the back surface of the die to the top surface of the package; and a plurality of second conductive elements on the bottom surface of the package.

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

Abstract: Methods, apparatuses, and systems related to an apparatus with an alignment moat are described. An example apparatus includes a conductive material divided into first and second portions which include top surfaces connected to each other, respectively, a first spacer surrounding the first portion of the conductive material, and a second spacer surrounding the second portion of the conductive material, where the top surface of the first spacer and the top surface of the second spacer are indented from the top surface of the first portion and the top surface of the second portion, respectively, to define an alignment moat.

Abstract: The invention provides a method of forming a perovskite film for an optoelectronic device, the method comprising: applying a perovskite precursor solution to at least one part of a hydrophilic region of a substrate, wherein the hydrophilic region is bounded by a hydrophobic boundary; allowing the perovskite precursor solution to spread over the hydrophilic region, wherein the perovskite precursor solution is retained within the hydrophilic region by at least a portion of the hydrophobic boundary; and drying the perovskite precursor solution to form a perovskite film on the hydrophilic region.

Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: Examples of devices for providing cooling solutions are described. One example device includes a boilerplate, a printed circuit board (PCB), one or more integrated circuit (IC) chips placed on the PCB, a thermal interface material (TIM), and one or more gaskets. The TIM is placed between the boilerplate and at least one IC chip of the one or more IC chips. The TIM is coupled to a surface of at least the IC chip that faces the boilerplate. The one or more gaskets are placed between the boilerplate and the PCB and encompassing the TIM. The one or more gaskets are configured to seal the at least one IC chip to provide a protective barrier for the TIM.

Abstract: The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.

Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.

Abstract: The present invention discloses an ultra-thin super junction IGBT and a manufacturing method thereof, comprising: a metalized collector; a P-type collector region located on the metalized collector; an N-type FS layer located above the P-type collector region; an N-type FS isolating layer located above the N-type FS layer; a first N-type epitaxial layer located above the N-type FS isolating layer and a second N-type epitaxial layer located above the first N-type epitaxial layer; and a MOS structure located in the second N-type epitaxial layer. According to the present invention, thinning the chip thickness reduces forward conduction voltage drop and switching losses, while reducing thermal resistance and improving current conducting capability.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Abstract: A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.