Patents Examined by Peniel M Gumedzoe
  • Patent number: 10734359
    Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes a first group of wiring layers of an internal redistributing layer (iRDL) providing a power supply voltage and a second group of wiring layers of another iRDL providing a ground voltage. The first group of wiring layers providing the power supply voltage from a first side of the semiconductor device to a second side of the semiconductor device opposite to the first side are at least partially separated by at least one cut portion between the first side and the second side.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hidenori Tobori
  • Patent number: 10734607
    Abstract: An organic light emitting diode (OLED) display panel and a encapsulation method of the organic light emitting diode display panel are provided. The encapsulation method includes steps of providing an OLED display panel having an OLED light emitting element layer in a display area thereof and an organic peeling layer in a non-display area thereof; laminating an inorganic film layer prepared in a full-surface coating method and an organic film layer only covering the display area sequentially; and peeling off the organic peeling layer together with the inorganic film layer on the surface of the organic peeling layer, so as to form a thin film encapsulation layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 4, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Kan Wang, Junyuan Wang, Hsianglun Hsu
  • Patent number: 10734469
    Abstract: A display device including a display panel; a panel support disposed on a lower surface of the display panel; a first circuit board connected to the display panel and disposed such that it overlaps with a lower surface of the panel support; and an adhesive member disposed between the panel support and the first circuit board and including a concave-convex profile on a first surface facing the panel support. The first circuit board and the panel support are at least partially coupled with each other by the adhesive member.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung Bae Song
  • Patent number: 10734331
    Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Rajarshi Mukhopadhyay
  • Patent number: 10734385
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 10727159
    Abstract: A structure for cooling an integrated circuit. The structure may include; an interposer cold plate having at least two expanding channels, each expanding channel having a flow direction from a channel inlet to a channel outlet, the flow direction having different directions for at least two of the at least two expanding channels, the channel inlet having an inlet width and the channel outlet having an outlet width, wherein the inlet width is less than the outlet width.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporatin
    Inventors: Thomas J. Brunschwiler, Timothy J. Chainer, Evan G. Colgan, Arvind Raj Mahankali Sridhar, Chin Lee Ong, Pritish R. Parida, Gerd Schlottig, Mark D. Schultz, Joel A. Silberman
  • Patent number: 10727233
    Abstract: An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Patent number: 10727158
    Abstract: A structure for cooling an integrated circuit. The structure may include; an interposer cold plate having at least two expanding channels, each expanding channel having a flow direction from a channel inlet to a channel outlet, the flow direction having different directions for at least two of the at least two expanding channels, the channel inlet having an inlet width and the channel outlet having an outlet width, wherein the inlet width is less than the outlet width.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Timothy J. Chainer, Evan G. Colgan, Arvind Raj Mahankali Sridhar, Chin Lee Ong, Pritish R. Parida, Gerd Schlottig, Mark D. Schultz, Joel A. Silberman
  • Patent number: 10717642
    Abstract: Electromechanical device structures are provided, as well as methods for forming them. The device structures incorporate at least a first and second substrate separated by an interface material layer, where the first substrate comprises an anchor material structure and at least one suspended material structure, optionally a spring material structure, and optionally an electrostatic sense electrode. The device structures may be formed by methods that include providing an interface material layer on one or both of the first and second substrates, bonding the interface materials to the opposing first or second substrate or to the other interface material layer, followed by forming the suspended material structure by etching.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 21, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Eugene A. Imhoff, Rachael L. Myers-Ward, Eugene Cook, Jonathan Bernstein, Marc Weinberg
  • Patent number: 10720482
    Abstract: A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 21, 2020
    Assignee: Japan Display Inc.
    Inventor: Toshihiro Sato
  • Patent number: 10720332
    Abstract: A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Deyuan Xiao
  • Patent number: 10713583
    Abstract: A method includes depositing a first layer on a portion of a first surface of a quantum hardware, the portion of the first surface comprising a set of wirebonds. The method further includes coupling the set of wirebonds to the first layer. The method further includes removing the first layer and the set of wirebonds from the first surface of the quantum hardware. In an embodiment, the first layer is an inert polymer in solution.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin O. Sandberg, Vivekananda P. Adiga, Robert Connelly
  • Patent number: 10714707
    Abstract: An organic light-emitting display apparatus includes a display substrate and a thin film encapsulation layer on the display substrate. The display substrate includes at least one hole, a thin film transistor, a light-emitting portion electrically connected to the thin film transistor, and a plurality of insulating layers. The light-emitting portion includes a first electrode, an intermediate layer, and a second electrode. The display substrate includes an active area, an inactive area between the active area and the hole, and a plurality of insulating dams. Each insulating dam includes at least one layer. The inactive area includes a first area different from a laser-etched area and a second laser-etched area.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sunkwang Kim, Kinyeng Kang, Suyeon Sim, Jonghyun Choi
  • Patent number: 10707073
    Abstract: Examples of a film forming method includes repeating first processing and second processing in this order a plurality of times, wherein the first processing supplies material-1 having one silicon atom per molecule onto a substrate, and then generates plasma while reactant gas is introduced, thereby forming a silicon oxide film on the substrate, and the second processing provides material-2 having two or more silicon atoms per molecule onto the substrate, and then generates plasma while no reactant gas is introduced, thereby forming a double silicon compound on the substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Yoshio Susa, Yuko Kengoyama, Taishi Ebisudani
  • Patent number: 10700120
    Abstract: This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 30, 2020
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi
  • Patent number: 10700000
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10700158
    Abstract: A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyungsoon Park, Ilgon Kim, Minjae Jeong
  • Patent number: 10692683
    Abstract: A novel photocathode employing a conduction band barrier is described. Incorporation of a barrier optimizes a trade-off between photoelectron transport efficiency and photoelectron escape probability. The barrier energy is designed to achieve a net increase in photocathode sensitivity over a specific operational temperature range.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEVAC, INC.
    Inventors: Kenneth A. Costello, Verle W. Aebi, Michael Jurkovic, Xi Zeng
  • Patent number: 10692952
    Abstract: The present disclosure provides an OLED substrate and a display device. The OLED substrate includes a base substrate, and a thin-film transistor, a first electrode, and a light-emitting layer arranged in sequence on the base substrate, in which the OLED substrate further includes a light-shielding layer arranged between an active layer of the thin-film transistor and the first electrode.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 23, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu Li, Zhanfeng Cao
  • Patent number: 10692824
    Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski