Patents Examined by Peniel M Gumedzoe
  • Patent number: 11404359
    Abstract: An integrated circuit package that includes a leadframe and a mold compound encapsulating at least a portion of the leadframe. The mold compound includes a cavity open at a bottom surface of the mold compound that exposes a bottom surface of the leadframe. A thermally conductive and electrically insulating isolation layer is locked within the bottom cavity of the mold compound and contacts the bottom surface of the leadframe.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefan Schwab, Alexander Roth
  • Patent number: 11404388
    Abstract: A device that includes a substrate including a plurality of metal layers, and a plurality of dielectric layers. The device further includes a first passive component including a first terminal, a second terminal, and a first body, mounted to the substrate on one of the plurality of metal layers. The first terminal is coupled to a first ground signal and the second terminal is coupled to a second ground signal such that the first passive component is shorted. The first passive component may be an inductor, a capacitor or a resistor. The first passive component is operable as a heat sink, a heat shield, an electromagnetic shield, or as a tuning inductor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Chun Liu, Peter Mark Davulis
  • Patent number: 11399438
    Abstract: The present disclosure provides a power module, a chip-embedded package module and a manufacturing method of the chip-embedded package module. The chip-embedded package module includes: a chip having a first surface and a second surface that are disposed oppositely; a first plastic member including a first cover portion and a first protrusion; and a second plastic member including a second cover portion and a second protrusion. A height difference discontinuous interface structure is formed between the top surface of the second protrusion and the second surface of the chip, which cuts off a passage for expansion of delamination at an edge position of the chip, thereby effectively suppressing generation of the delamination.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 26, 2022
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Qingdong Chen, Ganyu Zhou, Yan Chen, Xiaoni Xin, Pengkai Ji
  • Patent number: 11393775
    Abstract: The present disclosure provides a semiconductor a semiconductor device package includes a substrate, an electronic component disposed on the substrate, a package body disposed on the substrate and encapsulating the electronic component, and a capacitor disposed above the electronic component. The capacitor is exposed from the package body.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Wei Hsieh, Ming-Tau Huang, Yu-Chih Lee
  • Patent number: 11387174
    Abstract: A semiconductor device includes: a first semiconductor integrated circuit including at least a first terminal and a second terminal; a first lead frame connected to the first terminal; a second lead frame connected to the second terminal; and a mold resin covering the first semiconductor integrated circuit. The mold resin further covers the first lead frame with a portion of the first lead frame being exposed. The mold resin further covers the second lead frame with a tip of the second lead frame opposite to the second terminal being exposed. The mold resin includes a recess, and the recess is opened to expose only the portion and the mold resin.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Kawahara, Toshitaka Sekine, Hiroyuki Nakamura
  • Patent number: 11387161
    Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Patent number: 11387175
    Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Sanka Ganesan, Pilin Liu, Shawna Liff, Sri Chaitra Chavali, Sandeep Gaan, Jimin Yao, Aastha Uppal
  • Patent number: 11387181
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11387200
    Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Telesphor Kamgaing, Javier A. Falcon, Yoshihiro Tomita, Vijay K. Nair
  • Patent number: 11387159
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 12, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Patent number: 11380610
    Abstract: A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 5, 2022
    Assignee: MICRO MODULE TECHNOLOGY CO., LTD.
    Inventor: Fumikazu Harazono
  • Patent number: 11373931
    Abstract: The disclosure describes a lid allowing for a liquid thermal interface material (TIM) in a lidded flip chip package. The lid includes a reservoir structure so that a liquid system can be formed in the lidded flip chip package, allowing for a liquid TIM in the gap between the lid and the flip chip. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a tunnel for taking in a liquid material and releasing it again from and to the gap according to the change of the gap volume. The lid further includes an injection hole and a plug for filling and removing liquid into or from the gap and reservoir. The lid further includes a plurality of pins, which extrude downwards from the bottom surface of the lid so as to strongly bond with the substrate of the flip chip package through an adhesive.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: June 28, 2022
    Inventor: Yuci Shen
  • Patent number: 11373962
    Abstract: A semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 11373982
    Abstract: A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinji Yamashita
  • Patent number: 11373942
    Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 28, 2022
    Inventors: Junyoung Ko, Senyun Kim, Younghoon Ro
  • Patent number: 11348852
    Abstract: A semiconductor device includes an insulating circuit substrate including an insulating plate, a first metal layer formed on a top surface of the insulating plate, and a second metal layer formed on a bottom surface of the insulating plate, a heatsink on whose top surface the insulating circuit substrate is disposed; semiconductor elements disposed on the top surface of the first metal layer through a bonding material, and a case that encloses a perimeter of the insulating circuit substrate and the semiconductor elements. The first metal layer includes circuit patterns electrically connected to the semiconductor elements and an annular pattern formed to enclose the perimeter of the circuit patterns with a gap provided with respect to the circuit patterns. The second metal layer is disposed at a spot that surfaces the annular pattern. The housing is affixed to the annular pattern through an adhesive.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 31, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Takizawa
  • Patent number: 11348855
    Abstract: A semiconductor component includes: a semiconductor device; an insulating molded portion configured to encapsulate the semiconductor device; a terminal connected to the semiconductor device, the terminal being configured to project out from the insulating molded portion; and a cooler mounted with the insulating molded portion such that the semiconductor device is cooled; wherein a recessed portion is formed in a surface of the cooler on which the insulating molded portion is mounted so as to extend from a position facing the terminal to a position at inner side of an end portion of the insulating molded portion.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 31, 2022
    Assignee: CALSONIC KANSEI CORPORATION
    Inventors: Yutaka Satou, Yasuyuki Ooi
  • Patent number: 11348856
    Abstract: A memory sub-system can include multiple memory devices and a thermal cooling element. The thermal cooling element includes a bottom surface that is coupled to a top surface of each of the memory devices. Furthermore, the thermal cooling element further has a top surface that includes a protrusions that extend above the top surface of the thermal cooling element to dissipate heat that is generated from the memory devices.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Rolf Thornton Munson
  • Patent number: 11342306
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11342196
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen