Patents Examined by Peniel M Gumedzoe
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Patent number: 11737311Abstract: An organic light-emitting display apparatus includes a display substrate and a thin film encapsulation layer on the display substrate. The display substrate includes at least one hole, a thin film transistor, a light-emitting portion electrically connected to the thin film transistor, and a plurality of insulating layers. The light-emitting portion includes a first electrode, an intermediate layer, and a second electrode. The display substrate includes an active area, an inactive area between the active area and the hole, and a plurality of insulating dams. Each insulating dam includes at least one layer. The inactive area includes a first area different from a laser-etched area and a second laser-etched area.Type: GrantFiled: February 15, 2022Date of Patent: August 22, 2023Assignee: Samsung Display Co., Ltd.Inventors: Sunkwang Kim, Kinyeng Kang, Suyeon Sim, Jonghyun Choi
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Patent number: 11728298Abstract: A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: ROHM CO., LTD.Inventor: Koshun Saito
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Patent number: 11730036Abstract: A pixel arrangement structure, an organic light emitting diode display panel, a display device, and a mask plate assembly are disclosed. The pixel arrangement structure includes a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels. The positions of the sub-pixels do not overlap each other. One of the first sub-pixels is located at the center position of a first virtual rectangle. Four of the first sub-pixels are located at four vertex angle positions of the first virtual rectangle, respectively. Four of the second sub-pixels are located at the center positions of four sides of the first virtual rectangle, respectively. The first virtual rectangle is divided into four second virtual rectangles. The inside of each of the four second virtual rectangles comprises one third sub-pixel of the third sub-pixels.Type: GrantFiled: January 4, 2022Date of Patent: August 15, 2023Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Weinan Dai, Yang Wang, Yangpeng Wang, Benlian Wang, Haijun Yin, Haijun Qiu, Yao Hu
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Patent number: 11728229Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.Type: GrantFiled: June 2, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
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Patent number: 11721607Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.Type: GrantFiled: January 23, 2020Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Je-Young Chang
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Patent number: 11721559Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.Type: GrantFiled: May 23, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Hsien-Wei Chen, Chi-Hsi Wu, Der-Chyang Yeh, An-Jhih Su, Wei-Yu Chen
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Patent number: 11705421Abstract: Semiconductor devices including continuous-core connectors and associated systems and methods are disclosed herein. The continuous-core connectors each include a peripheral wall that surrounds an inner-core configured to provide an electrical path using uniform material.Type: GrantFiled: April 15, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Po Chih Yang, Po Chen Kuo, Chih Hong Wang
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Patent number: 11705381Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.Type: GrantFiled: July 14, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Chen, Hung-Yu Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11694941Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.Type: GrantFiled: May 12, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11694953Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.Type: GrantFiled: March 8, 2022Date of Patent: July 4, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Joo-Nyung Jang
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Patent number: 11694921Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.Type: GrantFiled: January 31, 2022Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11682605Abstract: Disclosed herein are integrated circuit (IC) packages with asymmetric adhesion material regions, as well as related methods and devices. For example, in some embodiments, an IC package may include a solder thermal interface material (STIM) between a die of the IC package and a lid of the IC package. The lid of the IC package may include an adhesion material region, in contact with the STIM, that is asymmetric with respect to the die.Type: GrantFiled: May 28, 2019Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Karthik Visvanathan, Shenavia S. Howell, Sergio Antonio Chan Arguedas, Peng Li
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Patent number: 11678520Abstract: A display apparatus is provided by the present invention, the display apparatus includes a first thin film transistor (TFT) disposed in a first pixel region and including a first semiconductor layer and a first gate electrode, where the semiconductor layer includes first source and drain regions; a second TFT disposed in a second pixel region adjacent the first pixel region and including a second semiconductor layer and a second gate electrode, where the second semiconductor layer includes a second source and drain regions; a first pixel electrode disposed in the first pixel region and including a first region where a first light-emitting layer is disposed and a second region extending from the first region and disposed on a first via hole; and a second pixel electrode disposed in the second pixel region and including a third region where a second light-emitting layer is disposed and a fourth region extending from the third region and disposed on a second via hole.Type: GrantFiled: December 6, 2021Date of Patent: June 13, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Junghun Yi, Seungkyu Lee, Wonkyu Kwak, Wonse Lee
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Patent number: 11670572Abstract: A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.Type: GrantFiled: November 18, 2021Date of Patent: June 6, 2023Assignee: ROHM CO., LTD.Inventors: Takumi Kanda, Masaaki Matsuo, Soichiro Takahashi, Yoshitoki Inami, Kaito Inoue
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Patent number: 11670597Abstract: A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Chuan Chang, Szu-Wei Lu
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Patent number: 11664286Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Patent number: 11658083Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.Type: GrantFiled: December 9, 2020Date of Patent: May 23, 2023Assignee: Texas Instruments IncorporatedInventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark, Steven Alfred Kummerl, Wai Lee
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Patent number: 11658089Abstract: The present invention relates to a semiconductor device including a printed circuit board, an electronic component, and a heat diffusion part. The printed circuit board includes an insulation layer, first and second conductor layers disposed respectively on first and second main faces of the insulation layer, a plurality of heat radiation vias penetrating from the first conductor layer to the second conductor layer on the insulation layer, and a conductor film covering inner side walls of the heat radiation vias. The heat radiation vias are provided at positions overlapping the electronic component and the heat radiation part in plan view viewed from the first main face of the printed circuit board. The heat diffusion part is disposed overlapping at least some of the heat radiation vias in plan view viewed from the second main face of the printed circuit board.Type: GrantFiled: December 11, 2018Date of Patent: May 23, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shuji Wakaiki, Shota Sato, Kenta Fujii, Takashi Kumagai
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Patent number: 11658244Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a contact over a fin structure, a gate spacer layer between the gate stack and the contact, a first mask layer over the gate stack, and a second mask layer over the contact. The first mask layer includes a protruding portion sandwiched between an upper portion of the second mask layer and the gate spacer layer.Type: GrantFiled: July 19, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11658086Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, the semiconductor devices being electrically connected to the interposer, a dam structure on the interposer extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices, and a stress relief on the interposer, the stress relief including an elastic member that fills gaps between the semiconductor devices and the dam structure.Type: GrantFiled: June 24, 2021Date of Patent: May 23, 2023Inventor: Dahee Park