Abstract: Provided is a planar power module with a spatially interleaved structure, including a top power substrate, a bottom power substrate arranged opposite to the top power substrate, and a plurality of interleaved switch units configured between the top power substrate and the bottom power substrate; wherein adjacent interleaved switch units are electrically connected through a current commutator so that the interleaved switch units form spatial position interleaving. Problems of uneven parallel currents and uneven heat dissipation in the power module are solved.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Abstract: The present invention relates to a molded air-cavity package. In addition, the present invention is related to a device comprising the same. The present invention is particularly related to molded air-cavity packages for radio-frequency ‘RF’ applications including but not limited to RF power amplifiers. Instead of using hard-stop features that are arranged around the entire perimeter of the package in a continuous manner, the present invention proposes to use spaced apart pillars formed by first and second cover supporting elements. By using only a limited amount of pillars, e.g. three or four, the position of the cover relative to the body can be defined in a more predictable manner. This particularly holds if the pillars are arranged in the outer corners of the package.

Abstract: To prevent deterioration of light incident/emission environment in a semiconductor device in which a transmissive material is laminated on an optical element forming surface via an adhesive. The semiconductor device includes a semiconductor element manufactured by chip size packaging, a transmissive material which is bonded with an adhesive to cover an optical element forming surface of the semiconductor element, and a side surface protective resin which covers an entire side surface where a layer structure of the semiconductor element and the transmissive material is exposed.

Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Abstract: The invention relates to a foil-based package with at least one foil substrate having an electrically conductive layer arranged thereon which is patterned to provide a first electrically conducting portion and a second electrically conducting portion, which is coplanar to the first electrically conducting portion, and a third electrically conducting portion, which is coplanar to the first electrically conducting portion, the first electrically conducting portion being arranged between the second and third electrically conducting portions. In accordance with the invention, the first electrically conducting portion is implemented to be a signal-guiding waveguide for high-frequency signals and the second electrically conducting portion, which is coplanar to the first electrically conducting portion, and the third electrically conducting portion, which is coplanar to the first electrically conducting portion, form an equipotential surface.

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, at least one die coupled to the substrate, and a stiffener coupled to the substrate, wherein the stiffener may include a stiffener frame, wherein the stiffener frame at least partially surrounds the at least one die. The stiffener may include at least one resilient member extending from the stiffener frame towards the at least one die, and the at least one resilient member may include a distal end that extends at a height above the substrate.

Abstract: The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.

Abstract: An electronic component mounting substrate includes an electronic component and a substrate that are electrically connected at a plurality of places on a bottom surface of the electronic component. At least two places of the plurality of places are electrically connected by bonding using a conductive adhesive, and places other than the at least two places of the plurality of places are electrically connected by soldering using a paste solder.

Abstract: The present disclosure provides a semiconductor component including a substrate, a plurality of metallic lines, a passivation layer and a spacer. The metallic lines are disposed on the substrate, the passivation layer is disposed over the substrate and the metallic lines, and the spacer is interposed between the substrate and the dielectric layer and between the metallic lines and the dielectric layer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

Abstract: Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.

Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area and in a material layer through a first mask. Second features are formed in a second product region of each die area and in the material layer through a second mask. Third features are formed in a third product region of each die area and in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area and in the material layer through a fourth mask. Fifth features are formed in an alignment region between the first, second, third and fourth product regions of each die area and in the material layer through the first, second, third and fourth masks. The first product region is free of the second, third, and fourth features.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.

Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.