Abstract: A configurable hardware for coupling to one of a plurality of hardware. Each of the plurality of hardware has a type. The configurable hardware includes a memory for storing an ID. The ID identifies the type of the hardware coupled to the configurable hardware.

Abstract: An apparatus and method for distributing interrupts to Intel® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system bus to a processor bus. The processor bus may include multiple IA-32 processors. The system bus may include any number of nodes. Interrupt transactions appearing on the system bus are converted by the bridge to interrupt signals. The bridge asserts the interrupt signals at one of two pins on a target IA-32 processor. One pin may be programmed to receive non-maskable interrupts and the other pin may be programmed to receive external interrupts. The bridge incorporates a priority and threshold mechanism. The bridge includes a buffer to store pending interrupt signals.

Abstract: A method and system for eliminating peripheral device conflicts in a multibus data-processing system which includes a Peripheral Component Interconnect (PCI) plus having multiple slots for interconnecting peripheral devices in an automatically derived configuration and an Industry Standard Architecture (ISA) bus having multiple slots for interconnecting peripheral devices in a user-selected configuration. Each slot included within the ISA bus includes a reset line for temporarily disabling an associated slot in response to an application of electrical power to the data-processing system in order to prevent power transition problems. In response to an existing or potential device conflict brought about by a user-selected configuration, a control signal is selectively applied to the reset line for one or more slots included within the ISA bus, temporarily disabling those slots during normal operation of the data-processing system.

Abstract: An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code.

Abstract: Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types.

Abstract: A local computer stores a current program such as an operating system or an application. A network server stores a latest program which is a latest version of the current program, and an identifier program for generating an identification corresponding to the latest program upon interrogation. An updater program is alternatively stored on the local computer or the network server for causing the latest program to be transferred from the network server to the local computer and replace the current computer program. The current program and the latest program each include a startup program configured to interrogate the identifier program, determine if the identification corresponds to the current program, and if the identification does not correspond to the current program, run the updater program.

Abstract: A power supply unit for a computer system is proposed which has at least one data memory unit, which provides data specific to the power supply unit, for system controllers in the computer system. This achieves the object of offering the capability of ensuring that the power supply unit is not overloaded or underloaded, or that an appropriate message is output to the outside world, without having to explicitly know all the possible operational situations even in the development phase of the power supply unit.

Abstract: It is necessary to authenticate each access by permitting or refusing it when a client makes an access to a server in a client-server system in which clients and servers are interconnected via a network. The client utilizes memory medium which stores both the server address and the memory medium's identification information. The client also uses a read-out device to fetch the contents of the memory medium and uses thus read out server address, to be connected to a desired server and then transmits the abovementioned read out identification information to ask for server access permission. The server, in response, when having received a server access permission request from the client, compares the memory medium identification information sent upon permission requesting to identification information stored beforehand and, based on the comparison results, sends the client the authentication of server access permission or refusal.

Abstract: Lock structures of a shared storage processor of a computing environment are copied. A copy operation for a lock structure of the shared storage processor is initiated. Although the lock structure is owned by an exploiter of the lock structure, one or more objects of the lock structure are copied via an operating system of the computing environment. The one or more objects are copied from the lock structure to another lock structure of the computing environment. Both lock structures may be located within the same shared storage processor or within different shared storage processors.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface has a memory with a high address memory section and a low address memory section. A plurality of directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses electrically is connected to the high address memory and a pair of low address busses is electrically connected to the low address memory. Each one of the directors is electrically connected to one of the pair of high address busses and one of the pair of low address busses. A front-end portion of the directors is electrically connected to the host computer and a rear-end portion of the directors is electrically connected to the bank of disk drives.

Abstract: A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM instigates a bandwidth adjustment associated with the bandwidth change request to one or more bus bridge portals.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. In order to reduce the delays in giving address bus grants, a bus arbiter for a bus connected to a processor and a particular port of the node controller parks the address bus towards the processor.

Abstract: A method of servicing a computer system without interrupting operation of the computer system, by connecting a computer component to a board of the computer system, detecting connection of the computer component to the system board using a control circuit, supplying power to the voltage input of the computer component in response to detecting the connection, and thereafter monitoring the power supplied to the voltage input of the computer component. The method may be used for core computer components such as CPU modules and voltage regulator modules. Power to the voltage input of the computer component is turned off in response to a determination that a current level of the power supplied to the voltage input exceeds a specified level. A fault signal is latched in an active state in response to the determination; the fault signal is reset when the component is removed from the system.

Abstract: A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shift register in communication with at least two processors and the destination request module. The destination request module in communication with one of the at least two processors in response to an input shift register status signal and a processor designation signal, the selected processor adapted to receive the parallel input data.

Abstract: Methods of booting a client data processing system attached to a control data processing system in a data processing network. At power-on or re-boot of a client system, an initial program load request is issued from the client system onto the network and responsive to the receipt of the initial program load request at the control system, bootstrap code is transferred to the client to cause the client to boot from operating system code stored on a mass storage device of the client; alternatively, bootstrap code is transferred to the client system to cause the client to boot from operating system stored on a mass storage device of the client, or bootstrap code is transferred to cause the client system to boot from the control system.

Abstract: A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.

Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Abstract: The connection system between electronic cards comprises at least a base card (CB) comprising a printed circuit having a set of tracks for transferring electric signals, at least two base connectors (CO2-CO5) connected on said set of tracks and each capable of removably receiving one of said electronic cards, means for amplifying signals connected on the printed circuit, and individual means of electricity supply connected on the printed circuit and capable of supplying the amplifying means and said electronic cards.

Abstract: A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet.