Abstract: A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a channel adapter at one PCI bus that issues read commands, a data source coupled to a second PCI bus, and a prefetch buffer that prefetches the blocks of read data. A prefetch counter posts the remaining number blocks to be read and transferred, posting the prefetch count at a storage location of a storage memory mapped to a prefetch location in the prefetch buffer. The prefetch count is written to the storage location by a prefetch count write command. The system for flushing stale data from the prefetch buffer comprises a key detector for sensing an unique identifier of the prefetch count write command.

Abstract: A method by which a plurality of users share access to a resource such as a common communications channel. Each user is assigned a priority and is provided with a non-uniform probability distribution function corresponding to that priority, with the sum of the several non-uniform probability distribution functions being uniform. Whenever a user wishes to access the resource, the user selects a random number according to its non-uniform probability distribution function and computes an access time based on the selected random number.

Abstract: A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

Abstract: A platform independent analysis architecture analyzes memory images for computer programs. The analysis architecture is platform independent in that it is not tied to a particular version of a computer program and is not dependent on the presence or absence of patches. In addition, the analysis architecture is not tied to the hardware architecture on which the analysis architecture runs. The analysis architecture dynamically determines data type definitions for a computer program to account for the hardware architecture on which the computer program runs, the version of the computer program that is running and the presence or absence of patches. As a result, accurate views of data types may be discerned at run time so that the views of the data types may be employed in analyzing memory images such as crash dumps and run time dumps. This analysis architectures greatly assists parties in debugging computer programs as a result.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.

Abstract: A method and system for communicating at least two data transfers on a common bus. Data is communicated between a simple device and a system processor or system connector via the common bus at a low data rate, and data is communicated between a more complex device and the system processor or system connector via the common bus at a high data rate. Low data rate communications are conducted by selectively varying the voltage level on the common bus at least between a low voltage range and a high voltage range, wherein the low voltage range represents a first data value and the high voltage range represents a second data value. High data rate communications can be conducted, simultaneous with the low data rate communications, by selectively varying the voltage level on the common bus at least between two voltage sub-levels within the low voltage range and between two voltage sub-levels within the high voltage range.

Abstract: A computer system operable to provide nodes of a cluster with a quorum resource includes a network interface controller, a mass storage device, a processor, and memory. The network interface controller is operable to send messages to the nodes via a network and receive messages from the nodes via the network. The mass storage device includes storage that is used to implement the quorum resource and that is accessible by the nodes via the network interface controller. The processor is operably coupled to the network interface controller and the mass storage device. The memory is operably coupled to the processor and includes instructions, which when executed by the processor, cause the processor to process a first message requesting ownership of the quorum resource that is received from a first node of the cluster via the network interface controller.

Abstract: A system comprising a supply voltage isolation module (50), and a battery detector (52), both responsive to a battery pin (41). The system further including a voltage detection module (54) responsive to a voltage supply pin (42), where the voltage detection module (54) compares a supply voltage from the voltage supply pin (42) to a threshold. The system also including control logic (56) responsive to the battery detector (52) and the voltage detection module (54). Also disclosed are methods for responding to connection of a battery (36) to a logic device (12), placing a logic device (12) into a low power state in response to connection of a battery (36) to the logic device (12), and detecting a battery condition for a logic device (12) having a battery pin (41).

Abstract: A system is disclosed for facilitating operation of a peripheral bus, such as a PCI bus, that operates at multiple clock speeds. The system includes an expansion slot controller that identifies the number of peripheral devices that have been installed in the expansion slots, and further determines whether these devices support high speed operation. The expansion slots transmit a signal indicating the presence of a peripheral device in the slot, and also transmit a signal indicating whether the device is operable at the higher clock frequency. Once the expansion slot controller determines this information, it decides whether operation at the higher frequency is supported by the peripheral devices and by the bus bridge. The expansion slot controller informs each peripheral device of what the operating frequency will be, and transmits a signal to the PCI bus bridge indicating if high frequency operation will be supported.

Abstract: A network bus for interconnecting a plurality of medical devices is described in which the devices are provided with modules adapted to communicate along the bus. Some of the devices are capable of assuming control over the bus with network master modules. A self-configuring capability is provided with which several network master capable medical devices automatically determine which network master is to take over control over the network bus and each individually is capable of controlling and operating the network. Each network master capable device has an extended network management module with which automatic master selection is achieved. This is done by monitoring or observing network communications for particular objects. Once such an object has been detected, a network master capable device is automatically selected to take over control on the basis of its priority.

Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

Abstract: The invention relates to a transmitting device and a bus system for the serial data transfer of binary data between at least two communication stations, which are coupled to one another via an individual bus line. The transmitting device of a communication station has a circuit for waveform setting. The circuit for waveform setting generates, from a data signal to be transmitted, an output signal having signal edges which are as far as possible in the form of sinusoidal half-waves. In order to generate the signal edges in the form of sine half-waves, an oscillator, a clock counter and a parallel D/A converter are connected in series one after the other. The output signal at the output of the D/A converter has stepped edges. An optimized output signal having signal edges in the form of sine half-waves can be generated by means of suitable dimensioning of the reference elements of the voltage divider of the D/A converter and also by means of a smoothing filter connected downstream of the D/A converter.

Abstract: A compact adapter for interconnecting a digital computer peripheral device that uses a Single Connector Attachment (“SCA”) to a conventional Small Computer System Interface (“SCSI”) bus. A SCA connector of the adapter mates with and engages a complementary SCA connector included in a peripheral device. The SCA connector is juxtaposed perpendicularly with a first face of a planar printed circuit board. A narrow width for the printed circuit board permits a disk drive mated with the adapter to fit within a space in a digital computer system adapted to receive a peripheral device. The compact adapter also includes an electrical power connector together with a first, conventional SCSI bus connector. Preferably, the adapter also includes a second, conventional SCSI bus connector having a different style from that of the first SCSI bus connector.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the PCI bus. This information can then be observed and used in a debugging process.

Abstract: The present invention relates to an application specific integrated circuit (ASIC) comprising an integrated central processor unit (CPU) (10), an integrated network interface control (NIC) (11) and at least one integrated input/output (I/O) device (13-16), and a transceiver circuit for buffering and amplifying SCSI signals from such an ASIC, whereby the outputs can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively. According to the invention at least one I/O device is an ATA (16) or SCSI (15) device, with ports for connection to an external transceiver. The invention also relates to such a transceiver circuit for buffering and amplifying SCSI signals on single direction lines from an ASIC, whereby the outputs to the SCSI bus can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively.

Abstract: The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a first lock state indicates that said resource is free. The requesting processor is placed on active standby if a second lock state indicates that said resource is busy. A lock includes a first and second lock state. The first lock state corresponds to a null value, and the second lock state corresponds to a non-null value.

Abstract: The present invention provides a breakpoint interrupt generation apparatus in a superscalar microprocessor, which can be implemented by small amount of hardware resources, thereby reducing required chip area.

Abstract: A self-configurable, adaptable and programmable (hereinafter “CAP”) I/O bus (15) is provided in a digital computer (11) to establish compatibility between the input/output bus of computer (11) and an incompatible input/output bus of an external module (12). Computer (11) includes a field programmable gate array (FPGA) (31) for translating the bus configuration used by module (12) to that employed by computer (11). Two preselected CAP I/O Bus conductors (17, 18) pass an identification number from the module (12) to computer (11) that points to the location of the information necessary to compatibly configure FPGA (31). This information, which includes a bus logic FPGA image file and a device driver, and may include a protocol driver, may be found in one of several locations, including onboard computer (11) in memory, onboard module (12), or at an external site such as a server (28) accessible via the Internet.