Abstract: The invention relates to the detection of the presence of a connector in a socket (10), the connector keeping a pin (13) of the socket to a a given level. The invention suggests to take advantage of this for detecting the presence of the connector, by trying to pull the pin to another-level (20, 21), and determining whether the level on the pin is the given level or the other level. For a socket for a WOL connector in the motherboard of a computer, the pin used is the wake signal pin, which is normally at a low level. Pull-up means are used to try and pull-up the voltage at the pin. This voltage is measured by scanning the status bit of the event register of the controller, to which the pin is connected. The voltage is pulled up only if no connector is plugged into the socket.

Abstract: A parallel SCSI host adapter integrated circuit includes a Bus Free management circuit having a plurality of input lines coupled to SCSI bus control terminals of said parallel SCSI host adapter integrated circuit; a Bus Free phase interrupt disable line; a clear line; a Bus Free phase status line; and a Bus Free phase interrupt line. The Bus Free management circuit automatically generates an active signal on said Bus Free phase status line following receipt of (i) one of a selection complete signal and a reselection complete signal on said plurality of input lines; and (ii) a Bus Free phase signal on said plurality of input lines. The parallel SCSI host adapter integrated circuit also includes a sequencer coupled to said clear line, to said Bus Free phase status line, and to said Bus Free phase interrupt disable line. The sequencer generates an active signal on said Bus Free phase interrupt disable line when a Bus Free phase is expected.

Abstract: In a 1394 network where a number of devices are connected, it is not easy to specify corresponding between a displayed device and a real device. Accordingly, “selection-candidate update processing, to find a new device and “processing for displaying candidates meeting set conditions” to display candidates which meet set conditions are provided, so as to display a device list window displaying selection candidates in a case where a set condition is, e.g., “printer”.

Abstract: A computer monitor includes a plurality of screen-control switches, an input/output circuit adapted to be connected to a computer, and a processor connected to the screen-control switches and the input/output circuit, and adapted to detect if a universal serial bus (USB) standard compliant-interface was established between the input/output circuit and the computer. The processor performs a hardware-based on-screen display routine to adjust screen characteristics of the computer monitor when the screen-control switches are operated and the USB standard compliant-interface is not detected. The processor generates a command that is assigned to an operated one of the screen-control switches and that is to be received by the computer via the USB standard compliant-interface when the USB standard compliant-interface is detected.

Abstract: A digital signal processing apparatus for processing a plurality of video signals and a plurality of audio signals is provided, and comprises a computer comprising a system bus and a main CPU connected to the system bus and an extension processor comprising a plurality of signal processing circuits for processing the plurality of video signals and/or the plurality of audio signals, and a local CPU for controlling the plurality of signal processing circuits so as to allow for the processing of the video signals and audio signals in real time. The extension processor further comprises an extension system bus extended from the system bus, a digital audio video (DAV) bus for transmitting the plurality of video signals and the plurality of audio signals between the plurality of signal processing circuits and a local CPU bus for transmitting control signals outputted from the local CPU.

Abstract: A method for lowering power consumption of a Universal Serial Bus (USB) device, comprising the steps of (A) detecting a frame comprising one or more indicators from an input data stream and (B) waking the USB device or continually operating in a suspend/sleep mode, in response to the one or more indicators.

Abstract: A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

Abstract: A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: In a computer system including one or more hosts coupled via a host bus to each other and a cached host memory, an Input/Output processor providing data to peripheral devices and an I/O bus disposed between the hosts and the Input/Output processor for transfer of information therebetween, an inbound queue structure receives message information from one of the hosts, and an outbound queue structure sends message information from the I/O processor to one of the hosts. Each of the queue structures comprises a pair designated as a free-list buffer and a post-list buffer. The free-list buffer of the inbound queue structure and the post-list buffer of the outbound queue structure are locally coupled to the hosts so that message information transfers between these two buffers and the hosts without incurring I/O bus read operations.

Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Abstract: A signal is transmitted from a sending chip to a first receiving chip in a communications ring via a first i/o set of the sending chip. A signal from the sending chip to a second receiving chip in the communications ring is transmitted via a second i/o set of the sending chip. The first i/o set corresponds to a first direction for the sending chip transmitting around the ring, and the second i/o set corresponds to a second direction for the sending chip transmitting around the ring. The transmitting via the first i/o set is for a circumstance where a number of chips interposed in the ring between the sending and receiving chips in the first direction is not greater than the number of chips interposed in the second direction. The transmitting via the second i/o set is for a circumstance where the number is greater.

Abstract: A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Abstract: A testing system includes a controller, a device driver for the controller, and a processor. The controller is operable to control a device coupled thereto. The device driver is operable to provide a generic interface for data transfers to and from the controller. The processor is coupled to coupled to the controller and is operable to execute a test script having a plurality of script commands. Moreover, the processor is operable to transfer test data to the controller via the generic interface of the device driver in response to executing a first script command of the plurality of script commands. The processor is also operable to receive status information from the controller via the controller generic interface.

Abstract: The interface circuit serves for connecting two apparatus by way of a bidirectional bus which comprises a data lead for transmitting data and a cycle lead for transmitting a cycle signal. The interface circuit consists of a circuit arrangement provided at each apparatus, which comprises a separating means for separating the data signal on the data lead and the cylce signal on the cycle lead in each case into a transmitting and a receiving branch, and which furthermore comprises in each case for the data lead and the cylce lead a bus driver having a differential transmitter and receiver. The data signals and cylce signals between the apparatus are transmitted via differential leads.

Abstract: A watchdog circuit for a microprocessor which has a reset input and a control output, which output, when operation is normal, periodically delivers, under program control, a signal (P0B2) of predefined duration (t1); and having a capacitor (32) that can be charged via a charging circuit; having a discharging circuit (40, 42), controlled by the control output, for said capacitor (32), for periodic discharge thereof during the predefined duration (t1); the charging circuit and discharging circuit being adapted to the program sequence of the microprocessor such that when the microprocessor is operating normally, charging of the capacitor via the charging circuit corresponds respectively to discharge thereof via the discharging circuit; so that the voltage at said capacitor rises and falls within a predefined voltage range; and having an apparatus (30), for monitoring the charge state of said capacitor (32), which, in the presence of a charge state thereof that does not occur in normal operation, effects a reset

Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

Abstract: A method of transferring data from a source device to a destination device via a source-control device connected to the source device and a destination-control device connected to the destination device includes the steps of transmitting a data-transfer-request signal from the source device to the source-control device, transmitting a data-transfer-acknowledge signal from the source-control device to the source device in response to the data-transfer-request signal, and transmitting a data-transfer-request signal from the source-control device to the destination-control device concurrently with the transmission of the data-transfer-acknowledge signal.

Abstract: The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.

Abstract: An electronic system having a central controller coupled to a plurality of remote transceiver modules by means of a serial bus. The modules are designed to remain in a sleep mode in which they consume no power until such time as a wakeup signal is sent over the bus by the central controller. Each module includes a source of power and power supply circuitry adapted to provide power for operating the module when the power supply circuitry is connected to the source of power. Each module further includes an energy detector coupled to the bus and adapted to connect the power supply circuitry to the source of power upon detection of energy, in the form of the wakeup signal, on the bus. Within each module is a microprocessor which responds to the provision of power by maintaining the connection between the source of power and the power supply after the wakeup signal has terminated and until such time as the module completes its assigned task.