Abstract: A protocol for superimposing status information onto an arbitration scheme between a first bus agent and a second bus agent. One embodiment of the arbitration scheme uses a grant signal and a request signal to arbitrate for use of a bus. The second bus agent may request to use the bus by asserting a request signal, which is received by a bus arbitration circuit. The bus arbitration circuit may or may not reside within the first bus agent. The bus arbitration logic acknowledges the request by asserting a grant signal, which is received by the second bus agent. A specific relationship between an address phase and the arbitration signals allows the first bus agent to pass status information to the second bus agent via the grant signal. The specific relationship between an address phase and the arbitration signals is a condition that typically does not occur where the arbitration signals are used to arbitrate for use of the bus.

Abstract: An apparatus, program product and method to dynamically control the bindings between Input/Output Adaptors (IOA's) and Input/Output Processors (IOP's) in a hierarchical I/O interface of a computer, such that an IOA can be dynamically reassigned from one IOP to another IOP such that the latter IOP takes over management of data transfer between the processing complex of the computer and the IOA from the former IOP. At least partial system availability is maintained in the computer during dynamic reassignment to minimize system downtime and simplify maintenance operations on the computer.

Abstract: A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet.

Abstract: An architecture for extending the Java security model to allow a user or administrator to grant permissions dynamically. By itself, the Java 2 security model does not allow additions to the collections of policy permissions after they have been loaded from the Java policy file. The inventive architecture allows Java applets and applications to dynamically prompt the user to grant a permission that does not exist in the Java policy file. If the user grants the permission, the present invention grants the permission for the ProtectionDomain to which the class asking for the permission belongs. Attributes for the dynamic permission may be set during runtime and saved across browser sessions.

Abstract: In a system to which a plurality of devices are connected, each device has heretofore required a connector for an AC adapter and a connector for a signal line. Further, in order to arrange it so that the amount of power supplied to the overall system will not exceed a limit value, it has been required to adjust the amount of power during system use by turning the power source of each device on or off. According to the present invention, a signal line for data transfer and a power line for supply of power in a system connecting a plurality of devices are consolidated in a single cable to make it possible to connect both lines to one connector of each device. The power controller of a certain device acquires the properties of a plurality of devices connected to this device, decides the optimum power distribution and controls the power controllers of each of the other devices.

Abstract: A computer system having a primary serial bus and one or more serial sub-busses separated from the primary serial bus by gating devices is described. By selectively enabling different gating devices (thereby coupling one serial sub-bus to the primary serial bus at a time), each sub-bus may support the maximum number of addressable devices. This, in turn, expands the effective serial bus address space of the computer system.

Abstract: A data server having a plurality of hot replaceable processing unit modules. Each module includes a motherboard having plugged therein: a CPU; a main memory; an I/O adapter card, and an interconnect printed board, electrically connected to the motherboard. A backplane has a first connector adapted for coupling to a DC power supply. The interconnect printed circuit board has a DC to DC converter connected to a second connector adapted to mate with the first connector to enable the processing unit module to be hot plugged into, or removed from, the backplane. The backplane has formed thereon a strip transmission line adapted to provide an Ethernet bus for interconnecting a plurality of the modules. A cable management system for a cabinet used to house the module includes at least one vertically extending channel disposed in the cabinet and a fastener adapted to open and enable the a cable to be inserted into the channel and close to retain such cable within the channel.

Abstract: To provide an information handling system and a method of controlling the same which allows the state of the system to be saved without destructing other user data on an external storage device. When a predetermined event occurs, the system saves hibernation information in a hibernation information storing area on a hard disk. A hibernation managing information storing area is provided in the outermost cylinder of the hard disk. A boot sector already exists in the outermost cylinder. Therefore, the hibernation managing information is written in the outermost cylinder after the boot sector has been sheltered to the hibernation information storing area. After such series of processes have been completed, the system shifts to a hibernation mode. On the other hand, when power feeding to the system is resumed, the hibernation information is read out to check whether or not the system was in the hibernation mode, etc.

Abstract: Method and program product operable on a computer for changing configuration/setup parameters in an embedded controller type X86 based computer system, the system characterized by the absence of any keyboard or video display, from a remote terminal. The power on self test sequence is modified to produce an externally detectable audio-visual signal indicating potential access through a port as an aspect of communicating configuration/setup from the remote terminal. Communication is established through the port of the embedded controller using a refined interrupt which selectively accepts keyboard data entered at a remote terminal and translates that data into configuration/setup parameters for the embedded controller.

Abstract: A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block.

Abstract: A bridge manager (bridge management equipment) is automatically determined. In a network, bridges 51 to 54 are configured by connecting portals 41 to 48 respectively connected to buses 11 to 15 and the different buses 11 to 15 are connected via the bridges 51 to 54. A value denoting the function of the bridge manager managing the portals 41 to 48 and equipment ID are stored in registers in each portal 41 to 48. One bridge manager is selected out of candidates 31 and 34 for a bridge manager based upon a value in the registers.

Abstract: A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.

Abstract: A device for extending functions of a computer connected thereto adds a new function to functions of an existing extension unit. The device includes a non-volatile memory and a new extension unit connected to the non-volatile memory and capable of being connected to the computer via a bus and to the existing extension unit. The new extension unit transfers what is stored in the non-volatile memory to the computer when the computer requests attribute information of the existing extension unit.

Abstract: A portable computer system with universal serial bus (USB) port or ports and a method for controlling power of the universal serial bus (USB) port is described. When the main power of the portable computer system is supplied from a battery rather than an alternating current (AC) adapter, the power of the universal serial bus (USB) port is automatically shut down. In addition, the power of the universal serial bus (USB ) port is completely shut down while the universal serial bus (USB) port is not used in response to a setting state of the universal serial bus (USB) port, thereby reducing unnecessary power consumption. Further, when an over-current is detected from the alternating current (AC) adapter or the battery, the power of the universal serial bus (USB) port is shut down, whereby damage to peripheral devices coupled to the universal serial bus (USB) port can be prevented.

Abstract: A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

Abstract: In an electronic system, an arithmetic device is provided between successive bus terminals or between successive modules, respectively, with an identification signal applied to a bus input that is routed from one bus terminal to the next bus terminal until the identification signal has passed through all bus terminals in order to identify the modules. The identification signal is subjected to an arithmetic operation and consequently changed in each arithmetic device before it is forwarded to the next bus terminal, wherein the “results of the operations” are used for identifying the individual bus terminals and the individual modules, respectively.

Abstract: The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is decoupled if no transition occurs.

Abstract: A display unit and method having a communication controller which is capable of bi-directionally communication with a video source. Video signals for video display are received from the video source and a memory stores at least display unit information, wherein the display unit information includes identifying information of the display unit. The communication controller communicates the display unit information to the video source and the display unit receives a signal from the video source that is generated based on at least a portion of the display unit information.

Abstract: A data fetching control mechanism of a host chipset is disclosed for determining a fetch size to fetch data from a memory subsystem of a computer system. Such a data fetching control mechanism comprises input logics coupled to receive variables of a read command, a bus frequency, a bus data width from a bus device; and an index table which generates fetch values indicating fetch sizes of data to be fetched from a memory subsystem on one side of a host chipset, via a primary bus, for the bus device on the other side of the host chipset, via a secondary bus.