Abstract: A write register access circuit 201 comprises data input terminals 1e01˜1e32, 32 pieces of first-stage flip-flops 1a01˜1a32, 16 pieces of second-stage flip-flops 1b01˜1b16 connected to the first-stage flip-flops 1a01˜1a16, an OR gate 1g, a flip-flop 1h, a NAND gate 11, 16 pieces of data selector circuits 1c01˜1c16, 32 pieces of gate circuits 1d01˜1d32, and 32 pieces of data output terminals 1f01˜1f32, and the write register access circuit 201 is connected to a CPU circuit 215 through an interruption request circuit Z. Therefore, when the write register access circuit 201 is included in an LSI, the write register access circuit 201 enables parallel processing between the CPU and the LSI without necessity of matching the instruction word length of the CPU and the bus width of the LSI, providing an internal bus width changing switch, and dealing with the problem at the software end of the CPU. Further, data transfer rate is increased.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Abstract: A module is provided for installation in a drive bay of a computer and is adapted to accommodate expansion circuitry rather than the electromechanical devices conventionally installed in drive bays. A system interface board is provided for insertion into an expansion socket on the computer's motherboard and is connected to the module, thus interfacing the expansion circuitry to the computer. The expansion circuitry can be greater in volume and is more accessible and more easily cooled than expansion circuitry installed in expansion sockets on the motherboard.

Abstract: A system includes a bus and devices capable of supporting multiple data transfer rates coupled to the bus. Each device includes a storage element storing a value indicating the supported transfer rates. A routine is adapted to update the value in the storage element of at least one device to indicate that one or more data transfer rates are unsupported by the device. The bus may include an Accelerated Graphics Port (AGP) bus.

Abstract: A computer system having bus controller operating code stored in a non operating system managed, extended portion of system memory. In one example, the operating code is executed by a bus controller for a computer bus conforming to the Universal Serial Bus (USB) specification. In one example, the bus controller operating code is stored in a portion of system memory that is located above the top system memory address reported to the operating system, thereby hiding the stored code from the operating system. In one example, the bus controller operating code is constructed during the startup of the computer system with a code construction routine. Storing bus controller operating code in a non operating system managed, extended portion of system memory provides a computer system greater flexibility in system memory usage.

Abstract: An apparatus and method for establishing construction information of an unmanaged Ethernet switch which is capable of readily replacing a memory according to a construction form of each option slot without opening or closing an outer casing. In the apparatus for establishing construction information of an unmanaged Ethernet switch, a first memory storing switch construction information, in the case where there is no option board mounted in an option slot, is positioned on a main board, and a second memory storing switch construction information, in the case where there is a option board in the option slot, is positioned on the option board, so that when there is no option board in the option slot, the first memory is automatically used, and when there is an option board in the option slot, the second memory is used.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: The present invention relates to a computer chip having integrated thereon a CPU, and a cache system being interconnected, and at least one synchronization unit. The chip is setable in one of at least two different running modes, a first one thereof being a DUT mode, and a second one thereof being a MONITOR mode. The MONITOR mode is complementary to the DUT mode. The chip additionally comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips being in complementary modes. Said signals comprises synchronization signals generated by said synchronization unit. The present invention further relates to a computer apparatus, and a debugging system both employing at least one such chip.

Abstract: Method and system aspects for check stop error handling are provided. A method aspect for check stop error handling in a computer system, the computer system comprising a plurality of components including a processor that supports an operating system and firmware, includes utilizing a service processor following a check stop error for error data retrieval and attempting a reboot of the computer system. The method further includes initiating firmware for failure reporting based on the error data retrieval when the reboot is successful.

Abstract: A communication link is used both as a primary communication link and as a subordinate link in a computer system. A first integrated circuit having a plurality of first functions and a second integrated circuit having a plurality of second functions, are connected via a first communication link. The first communication link includes a plurality of first logical pipes carrying transactions on the first communication link, each of the first logical pipes having a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. A second communication link is coupled to the first communication link and includes a plurality of second logical pipes carrying transactions on the second communication link, each of the second logical pipes has a source end and a target end. A target (or source) end of one of the first pipes is communicatively coupled on the second integrated circuit to a source (or target) end one of the second pipes.

Abstract: A post write buffer for a dual clock system which improves the utilization of host data bus (10) bandwidth is provided which consists of an address buffer (60), a data buffer (62), a first clock timing signal (22), a second clock timing signal (48), an address decoder (24), a first write enable circuit (72), and a second write enable circuit (74). The address-buffer (60) and data buffer (62). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder (24) determines which destination register byte will receive the data in the host data bus (10). The write enable circuits (72, 74) synchronize the clock signals (22, 48) and determine when the destination register is ready to receive the data from the data buffer (62).

Abstract: An exemplary embodiment of the invention is an interconnection system including a primary connector having a first detection contact coupled to a first voltage, a second detection contact coupled to said first voltage and a reference contact coupled to a second voltage. The interconnection system includes a secondary connector having a first contact, a second contact and a secondary reference contact. The second contact and secondary reference contact are electrically connected. The first contact makes electrical connection with the first detection contact, the second contact makes electrical connection with the second detection contact and the secondary reference contact makes electrical connection with the reference contact. When the second detection contact makes electrical connection with the second contact, the second detection contact is connected to the second voltage.

Abstract: A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

Abstract: A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus.

Abstract: An I/O device in the form of an internal dongle includes a body having connective structure being arranged to removably attach the body to a housing of an electronic device. The dongle also includes a circuit assembly that has an exterior connector on the body for electrically connecting to a second electronic device, a dongle circuit being electrically coupled to the external connector through the body, an electronic cable having a first end electrically coupled to the dongle circuit, and a second end being structured and arranged to connect to an electronic component of the first mentioned electronic device within the housing.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A method and system for monitoring and adapting to configuration changes in a data processing system having a known configuration, while power is applied thereto. In response to a configuration change in the data processing system, values are calculated for multiple system operating factors. An alert is provided to a user if at least one of said calculated values, among the multiple system operating factors, is not within a predetermined range of values for the multiple system operating factors. In addition, the operation of the data processing system is restricted to accommodate for any system operating factors which are not within the predetermined range of values, such that the data processing system is guarded from damage due to an unstable configuration.

Abstract: The present invention provides a multiple bus control device and others which can also be applied to access control by a signal having a directional propagation property for implementing various communication between/among modules. Each of plural modules makes a request for communication to a multiple bus control device by sending communication request information for specifying one or more communication partner modules to the multiple bus control device. The multiple bus control device checks an idle state of a module to be communicated and an idle channel in a multiple bus based upon received communication request information and permits communication between a module which sends communication request information using the idle channel and a communication partner module specified in the communication request information.

Abstract: The present invention relates to a method of in-band communication, outside the standard SCSI communication protocol, between SCSI bus repeaters and initiator devices. The present invention implements the communication mode during the message phase of the SCSI protocol and allows initiators on a SCSI bus to determine the number, location and status of SCSI repeaters accessible on the SCSI bus.

Abstract: An integrated circuit device adapted to be incorporated into a portable article having a memory, in particular of a card format. The device includes a central processor unit, at least one memory, at least one data input/output pad, n address bus lines connecting the central processor unit to the memory and/or to the input/output pad to carry address bits, and D data bus lines connecting the central processor unit to the memory and/or to the input/output pad for conveying data bits. At least one address line from the address bus and the data bus is associated with an additional line for conveying bits that are complementary to the bits conveyed over the address bus line or data bus line.