Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.

Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A computer-implemented method for a simulation of a printed circuit board includes dividing a layout of the printed circuit board into elements having the same size, detecting first elements that have at least two materials from the elements, calculating anisotropic attributes of the first elements and assigning the anisotropic attributes to each of the first elements, and calculating a warpage of the printed circuit board based on the anisotropic attributes of the first elements. The anisotropic attributes depend on physical properties according to directions of the first elements on the layout.

Abstract: A method including computing a multi-variable cost function, the multi-variable cost function representing a metric characterizing a degree of matching between a result when measuring a metrology target structure using a substrate measurement recipe and a behavior of a pattern of a functional device, the metric being a function of a plurality of design variables including a parameter of the metrology target structure, and adjusting the design variables and computing the cost function with the adjusted design variables, until a certain termination condition is satisfied.

Abstract: A multi-mode power supply system for a portable infusion device is provided, comprising a Battery I and an Battery II, the Battery I constantly charges the Battery II constituting a charging circuit, which adopts one of multiple charging modes including a basal-rate slow charging mode, a bolus-dose fast charging mode and a background charging mode depending on different drug infusion conditions; the Battery I powers the control unit independently, and the Battery II powers the driving unit independently; a unidirectional conduction circuit, a monitoring circuit and a detecting circuit are further comprised to ensure the normal operation of the power supply system under various circumstances.

Abstract: Examples of wireless charging of a computing system are described herein. In an example, a charging notification from a power transmit unit (PTU) in a power transfer field of the computing system may be received. In response to receiving the charging notification, it may be ascertained whether a near field communication (NFC) component of the computing system is in an active state for data communication. When the NFC component is in the active state, an input may be provided to switch the active state of the NFC component to an inactive state for disabling data communication through the NFC component.

Abstract: An electric vehicle charging assembly includes a cord reel, a cord reel locking mechanism, and a master control unit for selectively unlocking the cord reel in response to an authorization signal. The electric vehicle charging assembly monitors the rotational position of the cord reel to prevent unauthorized use, and to record or relay information related to the improper use or malfunction of the electric vehicle charging assembly.

Abstract: A substrate having a plurality of features for use in measuring a parameter of a device manufacturing process and associated methods and apparatus. The measurement is by illumination of the features with measurement radiation from an optical apparatus and detecting a signal arising from interaction between the measurement radiation and the features. The plurality of features include first features distributed in a periodic fashion at a first pitch, and second features distributed in a periodic fashion at a second pitch, wherein the first pitch and second pitch are such that a combined pitch of the first and second features is constant irrespective of the presence of pitch walk in the plurality of features.

Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Abstract: A magnetic sheet includes a first region and a second region disposed adjacent to each other on a same surface, wherein the first region includes first crack lines formed in a first direction, and the second region includes second crack lines formed in a second direction.

Abstract: This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. The computing system can compare the simulated wafer image against a target wafer image in a layout design to identify hotspots where the simulated wafer image deviates from the target wafer image. Based on the identified hotspots, the computing system can modify the target wafer image in the layout design, prioritize edge modification in a subsequent optical proximity correction process, or modify computation of image error, which drives the optical proximity correction process.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: A magnetic coil suitable for wireless power transfer comprises a layer of magnetically-permeable material and plural conductors that follow respective convoluted paths relative to the layer of magnetically-permeable material to form respective inductors. In use, the conductors have substantially equalized inductances based on the convoluted paths and interaction with the magnetically-permeable material. One way of achieving this is to place the conductors such that the overall proximity of the conductors to the layer of magnetically-permeable material along their respective lengths is substantially equal. In this way, the conductors are positioned substantially symmetrically with respect to the layer of magnetically-permeable material, such that an average distance of each individual section of the conductors proximate to the permeable layer is equal.

Abstract: An all-solid-state battery system comprising an all-solid-state battery comprising a positive electrode active material layer, a solid electrolyte layer, and a negative electrode active material layer, and a control device configured to control a charge-discharge voltage during use of the all-solid-state battery. The negative electrode active material layer includes alloy negative electrode active material particles. The amorphization degree of the alloy negative electrode active material particles is in the range of 27.8% to 82.8% and a ratio Z/W is in the range of 0.32 to 0.60, where Z is a controlled discharge capacity of the all-solid-state battery, and W is a theoretical capacity of the alloy negative electrode active material particles × a total weight of the alloy negative electrode active material particles × the amorphization degree.

Abstract: Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.

Abstract: A charge management system including a power distribution bus circuit for distributing energy from a power source to a load, and an intermediate energy storage circuit operably connected to a power distribution bus circuit for aiding in distribution of energy to the load. A charge management system controller may be configured to control the discharge of energy between the intermediate storage circuit and the power distribution bus circuit during one or more modes. Such a charge management system may enable the power distribution bus circuit to receive energy from the intermediate energy storage circuit before the power bus voltage drops in response to load demand, which may enable the power source to respond to perturbations in the power bus voltage and minimize inrush current from the power source. The system also may be used to soft-start high-power equipment, or absorb energy spikes associated with shut-down.