Abstract: An improved TCAD software tool includes a structure generator for generating a core single-pixel three-dimensional (3D) model including only front-end details of a single CIS pixel, a prototyping tool for generating modified CIS prototypes by automatically combining the core single-pixel 3D model with features and configurations included in selected modular templates, and a separate mesh generator for generating optical simulation models by generating optical meshes based on each CIS prototype's selected configuration. The modular templates include pre-configured optically-relevant (e.g., micro-lens and anti-reflection) structures, alternative (e.g., front-side illuminated or back-side illuminated, two-dimensional or 3D) pixel configurations, alternative array configurations, and alternative color filter patterns.

Abstract: A battery power table setting method for using battery power efficiently and preventing battery overcharge includes: a first table generation operation for generating a first table by measuring a maximum charging power that prevents an output of a battery from being more than a maximum allowable voltage when the battery having a predetermined SOC value is charged at a predetermined temperature for a predetermined time; a second table generation operation for generating a second table by measuring an SOC value at the time point that the battery reaches the maximum allowable voltage when the battery is charged with a predetermined power value at a predetermined temperature; a third table generation operation for generating a third table by calculating a second maximum charging power according to a predetermined temperature and a predetermined SOC value based on the second table; and a derating table generation operation for generating a derating table.

Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.

Abstract: A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

Abstract: In one embodiment, a device in a wireless power transfer (WPT) system receives data regarding a vehicle equipped with a vehicle-based charging coil configured to receive electrical power transferred from a ground-based charging coil of the WPT system. The device determines, based on the received data, a time at which the vehicle-based charging coil is expected to be in charging proximity of the ground-based coil. Based on the received data, the device determines a gap distance between the vehicle-based charging coil and the ground-based charging coil to optimize the transfer of electrical power from the ground-based charging coil to the vehicle-based charging coil when the coils are in charging proximity of one another. The device sends control instructions to an adjustment system to implement the identified gap distance in advance of the determined time by adjusting a height of the vehicle-based charging coil or the ground-based charging coil.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine a first sequence of signal transition representations of a first signal of a first module of a register level circuit design. The second module of the register level circuit design comprises the first module, arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of the first signal of the first module. The signal transition representations of a second signal are propagated from the second module to the first module using the first signal. The tool can determine whether a first mapping can be determined between the first sequence and the second sequence, where the second sequence is propagated through the first module.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: There is provided a secondary coil module receiving supply of electric power via a primary coil by contactless power transfer technique. The secondary coil module includes a core formed of magnetic material, the core having a tubular portion in the form of a tube and a bottom portion formed integral with the tubular portion in such a manner as to close an opening of the tubular portion formed at one axial end portion thereof, a storage battery accommodated within an accommodation space provided inside the tubular portion and configured to be charged by the power via the primary coil and a coil winding disposed outside the core and on the side of the bottom portion of the core.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

Abstract: Disclosed are battery management systems with control logic for battery state estimation (BSE), methods for making/using/assembling a battery cell with a reference electrode, and electric drive vehicles equipped with a traction battery pack and BSE capabilities. In an example, a battery cell assembly includes a battery housing with an electrolyte composition stored within the battery housing. The electrolyte composition transports ions between working electrodes. A first working (anode) electrode is attached to the battery housing in electrochemical contact with the electrolyte composition. Likewise, a second working (cathode) electrode is attached to the battery housing in electrochemical contact with the electrolyte composition. A reference electrode is interposed between the first and second working electrodes, placed in electrochemical contact with the electrolyte composition.

Abstract: A semiconductor structure includes: first and second active regions arranged in a first grid oriented in a first direction; and gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction; wherein: the first and second active regions are separated, relative to the second direction, by a gap; each gate electrode includes a first segment and a gate extension; each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?(?150 nm); and each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular. In an embodiment, the height HEXT is HEXT?(?100 nm).

Abstract: A mobile charging device may be used to move a battery or a power cord to a target device. The target device may be a vehicle or other equipment with a battery. Power from the power cord or battery in the charging device may be used to provide power to the target device to recharge the battery in the target device. The charging device may couple a power cord to the target device, may couple a connector in the charging device to the target device, or may use a wireless power transfer element such as a coil antenna to transfer power wirelessly to the target device. Sensors may be used to facilitate alignment between the charging device and target device. Sensors may also be used to dynamically detect and avoid foreign objects in the path of the charging device.

Abstract: A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.

Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.

Abstract: The present invention provides a structure of a clock distribution network and generation method thereof. The clock distribution network is distributed in multiple local circuit modules. The clock distribution network comprises a clock tree structure and clock mesh structures, wherein the clock tree structure is distributed at least between or among the multiple local circuit modules and has a root node which is a clock access point of the clock distribution network. The clock mesh structures are distributed within at least one local circuit module at least according to a proportion of clock nodes in the local circuit module, a proportion of sequential circuits connected by clock in the local circuit module, a ratio of a total length of clock routing wirings in the local circuit module to a perimeter of the local circuit module, and a proportion of timing violation paths in the local circuit module.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).