Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Abstract: A wireless charging unit for an electric vehicle is provided with a metal enclosure to shield a high-power switching noise environment enclosed within the unit. A wireless power transfer system includes the wireless charging unit on the electric vehicle side that receives power wirelessly from a charging base. In addition to a high-power switching network, the wireless charging unit may include a wireless communication system for wirelessly communicating control messages to the charging base. The metal enclosure may include a cutout region having a plastic cover underneath which an antenna may be mounted to establish wireless communication with the charging base from within the metal enclosure.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.

Abstract: Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.

Abstract: One aspect is an analysis system that includes a processor operably coupled to a memory and configured to perform a method. The method includes defining a set of workloads for a targeted multi-core computer system based on a plurality of metrics of interest to profile. A plurality of workload-to-core mappings is generated for the workloads on the targeted multi-core computer system. The workloads run on the targeted multi-core computer system based on the workload-to-core mappings to produce a mapping of the workloads to the metrics of interest as experimental data. A statistical analysis is applied on the experimental data to define a plurality of metric profiles for the targeted multi-core computer system.

Abstract: A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.

Abstract: Using high level synthesis (HLS) and linked hardware description language (HDL) libraries to implement a circuit design includes generating, using computer hardware, a data flow graph from a model that includes an HDL model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code, and dividing, using the computer hardware, the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block. Using the computer hardware, a first HDL core is generated from the first sub-graph, synthesizable program code is generated form the second sub-graph, HLS is performed on the synthesizable program code to generate a second HDL core, and the circuit design is generated including the first HDL core connected to the second HDL core.

Abstract: Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

Abstract: A method for optimizing a binary mask pattern includes determining, by a processor, an evaluation value based on a comparison between a design pattern and a substrate pattern simulated based on the binary mask pattern. The method also includes, based on the evaluation value, using, by the processor, a gradient-based optimization method to generate a first adjusted binary mask pattern. The method also includes determining, by the processor, a first updated evaluation value based on a comparison between the design pattern and a first updated substrate pattern simulated based on the first adjusted binary mask pattern. The method also includes, based on the first updated evaluation value, using, by the processor, a product of a Hessian matrix and an arbitrary vector to generate a second adjusted binary mask pattern. The method also includes simulating, by the processor, a second updated substrate pattern based on the second adjusted binary mask pattern.

Abstract: Disclosed techniques conform standard cells in an integrated circuit design into a valid template pattern using a template-based approach to standard cell design. The template architecture stores valid patterns of circuit elements for the design. A Boolean expression comprising an aggregated set of Boolean assertions can be generated for each different combination of cell shape features and edge locations with the cell design to compute a solution that matches with a valid pattern in one of the templates. If the solution evaluates to a Boolean TRUE result, the cell shape(s) can be modified in accordance with the solution. If not, the granularity can be updated by incrementing an “adjustment neighborhood” value and iterating the computations for shape features and edge locations using the updated values for the analysis until a Boolean TRUE result is found or it is determined there is no solution for the set of expressions.

Abstract: A mobile terminal including a terminal body comprising a battery; an adaptor connector formed at one side surface of the terminal body and to which a power supply adaptor is connected; a plurality of charging units configured to charge the battery between the adaptor connector and the battery; and a controller configured to generate a control signal for controlling each of the plurality of charging units.

Abstract: An ECU obtains an OCV and an internal pressure, obtains a first estimated value of an SOC corresponding to the time of charging and a second estimated value of the SOC corresponding to the time of discharging using the obtained OCV and a first correspondence, obtains a third estimated value of an SOC corresponding to the time of charging and a fourth estimated value of the SOC corresponding to the time of discharging using the obtained internal pressure and a second correspondence, estimates the SOC using at least one of the first or the third estimated value when a first difference between the first and the third estimated value is less than a second difference between the second and the fourth estimated value, and estimates the SOC using at least one of the second or the fourth estimated value when the second difference is less than the first difference.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.

Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.

Abstract: A method of designing a semiconductor device including a memory device, a buffer, and a plurality of head circuits connected to the buffer is disclosed. The method includes generating a layout pattern of a power line of the semiconductor device, generating an improved layout pattern of a pre-routing line that connects the buffer to the head circuits, and generating a layout pattern of signal lines of the semiconductor device. The signal lines include both normal signal lines and signal lines for a central clock of the semiconductor device. A layout of the semiconductor device includes a plurality of layers.

Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.

Abstract: A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Abstract: An electronic breadboard system may include a computing device including a display screen. The display screen has a first portion to display an electronic circuit model and a second portion directly adjacent to the first portion. The electronic breadboard system also includes a translucent breadboard on the second portion of the display screen. The translucent breadboard includes a translucent face plate having a rectangular grid of openings exposing a plurality of contacts. The plurality of contacts are arranged lengthwise along each row of the rectangular grid of openings and orthogonal to a transparent back plate coupling the plurality of contacts to the translucent face plate. The electronic breadboard system includes a graphics controller. The graphics controller may illuminate a row opening and/or a column opening of the translucent breadboard to direct placement of electrical components of a computer model in response to user interaction with the electronic circuit model.