Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A method and a device for generating boundary-scan interconnection lines are disclosed. In the method, the boundary scan test model is established according to boundary scan components and intermediate components on least one test card and a unit under test (UUT) board, and connection relationships therebetween; the boundary scan nets of the boundary scan test model are constructed; the boundary scan paths of each boundary scan net are generated, and a path establishment condition of each boundary scan path is obtained; and the boundary scan paths are filtered and integrated, and the filtered and integrated boundary scan paths are divided according to the path establishment conditions of filtered and integrated boundary scan paths, into subtests which each has at least one boundary-scan interconnection line. As a result, the accuracy and high coverage of a path search operation can be guaranteed.

Abstract: Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.

Abstract: A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE.

Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques execute a sequence of instructions to identify at least a layout or a portion thereof and identify a plurality of layout devices in the layout or the portion thereof. These techniques further generate a figure group at least by enclosing the plurality of layout devices within a boundary for the figure group. These techniques may modify layout devices in a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

Abstract: A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command.

Abstract: Methods of controlling an across-wafer profile of a semiconductor process, as well as related systems and computer program products. A target profile of a semiconductor process over a radius of a wafer is fit to a polynomial. A plurality of gain matrices between a first plurality of process inputs and a plurality of polynomial coefficients of the polynomial are determined. An offset is estimated between the plurality of polynomial coefficients and an effect of the first plurality of process inputs. An objective function is defined as an integral of a squared deviation between an estimated profile and the target profile over the radius of the wafer. A second plurality of process inputs are mapped to the objective function by vector convolution using the plurality of gain matrices. The objective function is solved to optimize the second plurality of process inputs.

Abstract: Computing assemblies, such as blade servers, can comprise a plurality of modular computing elements coupled onto an associated circuit board assembly. Assemblies and systems having enhanced individual computing module placement and arrangement are discussed herein, as well as example systems and operations to manufacture such assemblies. In one example, a method includes executing a performance test on a plurality of computing modules to determine at least variability in power consumption across the plurality of computing modules, and binning the plurality of computing modules according to graduated levels of the variability in power consumption. The method also includes selecting from among the graduated levels for placement in an assembly of ones of the computing modules in a progressively lower power consumption arrangement with relation to an airflow of the assembly.

Abstract: A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

Abstract: A power source device, capable of charging a power storage device using power from a power source, is realized with a configuration capable of suppressing the generation of heat and noise. The power source includes a controller that determines an output state of a power storage device on the basis of a detection value detected by a voltage detection circuit. When the output state of the power storage device corresponds to a prescribed high-voltage state when prescribed charging conditions are satisfied, the controller causes only a first charging circuit, among the first charging circuit and a second charging circuit, to operate. When the output state corresponds to a prescribed low-voltage state, the controller causes only the second charging circuit to operate.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.

Abstract: A power delivery device includes at least one solar panel, a battery pack comprising at least one battery, and a heater, wherein the device is configured to measure the temperature of the battery pack and power the heater to heat the battery pack if it is too cold for optimal charging.

Abstract: A method for automatically finding a verification test of a plurality of verification tests that were executed in a verification process of a design under test (DUT) that satisfies a criterion, may include using a processor, obtaining from a user a criterion that relates to one or more test actions; using a processor, obtaining a log with logged execution data that includes start and end times for each action of each of the tests of the plurality of verification tests during an execution run of that test; and for each test of the plurality of verification tests, using a processor, determining from the logged data whether that test satisfies the obtained criterion, and if a test of the plurality of verification tests was determined to satisfy the obtained criterion, using a processor, executing that test on the DUT.

Abstract: A method includes determining topographic information of a substrate for use in a lithographic imaging system, determining or estimating, based on the topographic information, imaging error information for a plurality of points in an image field of the lithographic imaging system, adapting a design for a patterning device based on the imaging error information. In an embodiment, a plurality of locations for metrology targets is optimized based on imaging error information for a plurality of points in an image field of a lithographic imaging system, wherein the optimizing involves minimizing a cost function that describes the imaging error information. In an embodiment, locations are weighted based on differences in imaging requirements across the image field.

Abstract: A battery charging method and apparatus are provided. The battery charging apparatus receives a desired charging time of a battery, generates charging currents of charging steps to charge the battery based on the desired charging time, acquires a charging limit condition including an internal state condition and a maximum charging time for each of the charging steps based on the desired charging time and an electrochemical model of the battery, and generates a charging profile including the charging currents and charging times of the charging currents based on the charging limit condition.

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).