Abstract: An integrated circuit, for example, a system-on-a-chip is disclosed. The integrated circuit includes a timing synchronisation unit including a hardware timer, for example, a gPTP timer. The integrated circuit also includes a non-Ethernet network interface, for example, a PCIe interface, for communicating with another integrated circuit having another hardware timer. The timing synchronisation unit is configured, in response to receiving a timing trigger from the other integrated circuit, to capture a local time t2. The timing synchronisation unit is further configured to provide the local time t2 to a processor for the processor to compute a timing offset between a remote time t1 of the other hardware timer which generated the timing trigger and the local time for time synchronisation.

Abstract: Example approaches for customization of thermal and power policies in computers, are described. In an example, a microcontroller of a computing system, also referred to as system, validates thermal policy custom data stored in a firmware storage medium of the system, in response to a supply of power to the system. On a successful validation of the thermal policy custom data, thermal control settings is updated with a customized thermal policy included in the thermal policy custom data. In response to initiation of a boot operation of the system, a processor of the system validates power policy custom data stored in the firmware storage medium. In response to a successful validation of the power policy custom data during the boot operation, the processor updates power control settings of the system with a customized power policy included in the power policy custom data.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: Disclosed is an electronic apparatus, including: a storage; and a processor configured to execute a first execution code based on first configuration information in response to an execution event of a program including the first execution code and the first configuration information stored in the storage, update the program by replacing the first execution code and the first configuration information with a second execution code and second configuration information in response to an update event of the program, and update the first configuration information to the second configuration information while maintaining the first execution code in response to the update event of the first configuration information.

Abstract: Described herein are methods, systems, and computer-readable storage media for generation of a secure and dynamically mutable operating system. Techniques include receiving a request to execute an application causing instantiation of an operating system by identifying one or more needed modules that include core kernel modules and operating system service modules that are dynamically plugged-in or unplugged based on the execution of the application. Techniques may further include assigning a separate memory space with a separate virtual address for each of the one or more modules, generating a unique cryptographic key for each of the one or more modules, storing each virtual address and corresponding unique cryptographic key together. Further the operating system generation system encrypts each of the one or more modules using their corresponding unique cryptographic key.

Abstract: A method for managing a chassis includes obtaining, by an enclosure controller of the chassis, a power supply application to the chassis using a power supply interface, wherein the power supply interface is operatively connected to a plurality of power supplies, initiating a boot-up of a kernel of the chassis in response to the power supply application, initiating a parallel boot task using the power supply management temporary namespace to identify a power supply of the plurality of power supplies, initiating a mounting of a boot-up file system, and initiating a user space boot-up using the boot-up file system, wherein the user space boot-up and the parallel boot task are initiated in parallel.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: A slave device (10) includes a frequency synchronization unit (11) configured to generate frequency control information synchronized with a frequency of a synchronous Ethernet (registered trademark) signal received from a master device (20), a time synchronization unit (12) configured to generate time control information synchronized with a time based on a time packet received from the master device (20), and a time synchronization signal generation unit (13) configured to generate a time synchronization signal based on the frequency control information and the time control information. The frequency synchronization unit (11) includes a frequency synchronizing PLL including a DCO (11a) configured to output the frequency control information, and the time synchronization unit (12) includes a time synchronizing PLL including a DCO (12a) configured to output the time control information.

Abstract: A method includes operating at least two inverters connected to a direct current network. Each inverter includes a control unit connected to a common communication bus and in each case at least one switching element, which is controlled by the control unit of the inverter with a clock signal. The common communication bus is connected to at least one further control unit, which in each case sends a message of a message type via the communication bus at different points of times. The reception of one of the messages of the message type in the control units of the inverters triggers a synchronization of their clock signals.

Abstract: A device for correcting a time parameter in a first node in accordance with a second node is provided. The device includes a clock pulse generator unit configured to provide periodic clock pulses in the first node. The device further includes a peripheral unit configured to decode symbols of an asynchronously transmitted telegram from the second node and to measure a number of clock pulses during the transmission of a symbol sequence of consecutive symbols of the telegram. The device also includes a correction unit configured to correct the time parameter as a function of a ratio of the measured number of clock pulses and the number of consecutive symbols in the symbol sequence.

Abstract: Disclosed are methods and systems to improve the time synchronization of power distribution systems and/or other distributed device networks. The disclosure relates to nesting selection algorithms to elect a grand master clock from among groups of devices in a network.

Abstract: A submodule for conversion of DC power capable of a plurality thereof being connected in series and used for DC-DC conversion in accordance with the present invention comprises: a power switching element for switching DC power supply to convert a source of DC including voltage transformation; a DC capacitor for storing DC power opened or closed by the power switching element; a power supply unit for supplying power required to drive the submodule from the DC capacitor; a submodule controller for controlling whole operation of the submodule; memory for storing data required for operating the submodule controller; and a communicating unit for performing data communication with an external device; wherein the submodule controller may perform a program update during a start sequence of the submodule or during a stop sequence thereof, while DC-DC conversion is operated.

Abstract: A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.

Abstract: A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

Abstract: A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a validation signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the validation signal. The first starting voltage is lower than the second starting voltage.

Abstract: A slave device continuously transmits a plurality of tuning blocks to a host device at intervals defined by a clock period between a plurality of data blocks at the time of transmitting the plurality of data blocks and by a clock period defined by a data structure of the plurality of tuning blocks.

Abstract: Timekeeping on a computing device is deterministically performed by implementing two successive calls to a time function that returns current time based on a continuously running counter that is maintained in one or more cores of the device's CPU. The same fixed time computation parameters are used in each call, with the single variable being a value that is read from the counter. For the initial call to the time function, the processor optimizes the instruction execution by predicting the function's execution path based on observed patterns. As the instructions and data are already cached, and the processor has the results of the prior execution path prediction, the subsequent call executes quickly and predictably relative to the initial call while the processor remains in a working (i.e., non-sleep) state. The series of calls provides a deterministic time computation with improved accuracy by mitigating the unpredictability of processor sleep state delays.

Abstract: A system incorporating a smartphone and an add-on device coupled to each other via combined data/power interface, the smartphone having a rechargeable battery connected to battery protection circuitry and the add-on device optionally having a rechargeable battery connected to battery protection circuitry as well, the combined data/power interface having one or more data pins for transferring data between the smartphone and the add-on device, one or more regulated power delivery pins, and one or more protected-battery power delivery pins, wherein the regulated power delivery pins are used to charge the battery of the smartphone from an external charger coupled to the add-on device, the batteries are connected to the battery protection circuitries that is configured to protect the battery by cutoff or limit the current or voltage on the battery electrodes, and the protected-battery power delivery pins are connected to the battery protection circuitries of the smartphone or add-on device.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: The present disclosure provides a signal transmission method and a signal transmission device, which are applied to a digital circuit including a plurality of circuit modules connected in series, and each circuit module is configured to perform corresponding operation processing based on a first clock signal provided by a first clock. The method includes: under driving of a second clock signal provided by a second clock, transmitting a first signal output by a current circuit module to a target circuit module in response to reception of the first signal, the first signal is a signal output by the current circuit module when operating based on the first clock signal, transmission of the first signal is completed within a current clock cycle of the first clock, and a clock rate of the second clock is greater than that of the first clock.