Abstract: Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.

Abstract: A computer power supply assembly (PSA) is provided. The PSA comprises an AC/DC power supply unit (PSU) and a DC/DC converter module. The DC/DC converter module is attached to the AC/DC power supply unit via conductor which may be a conductive bridge that holds the AC/DC PSU in fixed relation to the DC/DC converter module, or may be a conductive cable with, for example, a twist connector. The DC/DC converter module is replaceable and interchangeable. Different types of DC/DC converter modules having different numbers and combinations of connectors for attachment to the electronics system devices and different wattage and efficiency can be electrically connected to the PSU via the one conductor.

Abstract: Systems and methods for burst power limit control in heterogenous computing platforms are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices; and a memory coupled to the heterogeneous computing platform, where the memory includes firmware instructions that, upon execution by at least one of the plurality of devices, causes the at least one device to operate as an orchestrator configured to: compare a current power level used by a selected device against a burst power limit; and in response to a determination that the current power level exceeds the burst power limit, control the selected device to reduce the current power level.

Abstract: A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.

Abstract: Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Abstract: Disclosed embodiments are related to techniques for powering compute platforms in low temperature environments. Embodiments include a preheating stage that is added to a power up sequence. The preheating stage may include a force-on stage and a force-offstage. During the force-on stage, all power rails of target components are forced to an ON state so that the target components consume current. When a target operating temperature is reached, the power rails of the target components are turned off, which causes the target components to revert back to their initial (pre-boot) state allowing the normal boot process to take place. Since the target components are now heated up, the boot process can execute faster than when the target components were cold. Other embodiments may be described and/or claimed.

Abstract: A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

Abstract: Method for time synchronization in a network between at least one master and at least one slave, which is an interrupt-capable network component and uses a timer, which accesses a slave time to generate at least one interrupt recurring at a predefined cycle duration, at a respective trigger point in time that is synchronized with the slave time. When a synchronization message arrives, a time offset between the master time and the slave time is determined in the slave, and a time fraction is determined from the time offset, which corresponds to an integer multiple of the predefined cycle duration of the at least one interrupt. An interrupt offset is then determined from the time fraction and the time offset. At least one time jump is carried out by a synchronization unit in the slave to correct the time offset.

Abstract: An electronic device according to an embodiment may include: a battery; a connector including multiple pins; and at least one processor, and wherein the at least one processor is configured to: identify an external electronic device electrically connected through the connector, identify, among at least two supportable current values, a current value of power to be supplied to the external electronic device, and supply power of the battery to the external electronic device through the connector based on the identified current value.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: The disclosure provides a microcontroller which has an internal timing device for generating an internal clock signal, at least one terminal contact for receiving an external clock signal, a clock changing device and a timer module, which is electrically conductively connected to the at least one terminal contact and to the internal timing device and, after the microcontroller has been switched on, is set up to determine a frequency of the external clock signal by means of the clock signal, and to determine at least one parameter by means of which the clock changing device can be set up to change the external clock signal into a useful clock signal with a predefined frequency.

Abstract: An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block.

Abstract: Systems and methods for managing performance in heterogenous computing platforms of IHS (Information Handling Systems) are described. In an illustrative, non-limiting embodiment, a heterogeneous computing platform includes devices and a memory storing firmware instructions. Based on execution of these firmware instructions by a respective device, a corresponding firmware service is provided such that one of the devices operates as an orchestrator. The orchestrator receives reports of changes in context of operation of the IHS by a user and based on the change in user context, determines responsiveness settings that are mapped to the reported user context, where the responsiveness settings adjust thread management policies by one or more processors of the heterogeneous computing platform. The orchestrator configures the one or more processors of the heterogeneous computing platform based on the responsiveness settings, and thus adjusts the performance of the IHS in response to the change in user context.

Abstract: Various aspects of methods, systems, and use cases include coordinating actions at an edge device based on power production in a distributed edge computing environment. A method may include identifying a long-term service level agreement (SLA) for a component of an edge device, and determining a list of resources related to the component using the long-term SLA. The method may include scheduling a task for the component based on the long-term SLA, a current battery level at the edge device, a current energy harvest rate at the edge device, or an amount of power required to complete the task. A resource of the list of resources may be used to initiate the task, such as according to the scheduling.

Abstract: A Power-over-Ethernet (POE) powered device (PD) may be coupled to two power sourcing equipments (PSEs), a PSE and an additional PSE. The PSE may exchange a transport layer protocol communications with the additional PSE. The communications comprising a first communication from the PSE to the additional PSE indicative of a PoE configuration of the PSE and a second communication from the additional PSE to the PSE indicative of a PoE configuration of the additional PSE. The PSE may create a power availability table based on the communications. The PSE may detect occurrence of an event comprising at least one of a change in the power availability table or a change in ability of the PSE to provide power to the PD. On occurrence of the event, the PSE may send additional communications to the additional PSE, requesting to adjust its power allotment for the PD.