Abstract: A system in accordance with present embodiments includes an amusement park system having one or more hardware components and a controller. The controller includes a memory device having a game layer and a software layer stored thereon. The game layer includes game logic, and the software layer includes a game API communicatively coupled to the game layer, a wrapper API communicatively coupled to the game API, and multiple wrappers communicatively coupled to the wrapper API. The controller further includes a processor configured to execute instructions to cause the processor to receive a signal indicative of a change in the hardware components, and, based on the signal indicative of the change in the hardware components, communicate with the hardware components via a wrapper to receive an input from the hardware components, or drive operation of the hardware components.

Abstract: Two clocks, a fast clock and a slow clock are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clock. Each of these gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock, such that the gap between the two frequencies may be kept to a manageable level so as to reduce transients upon switching between the two clocks. The system switches between the gears as required. In response to a determination to increase the frequency of the clock signal, a higher gear is selected at which the maximum and minimum frequencies defined for that gear are higher than the previous selected gear.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: A timing generator, a timing generating method and an associated control chip are provided, wherein the timing generator includes a receiving circuit, a transmitting circuit coupled to the receiving circuit, and a control unit respectively coupled to the receiving circuit and the transmitting circuit. The receiving circuit may be configured to receive a timing data set from a storage device. The transmitting circuit may be configured to select a specific signal type within multiple signal types according to the timing data set, and output an output signal having the specific signal type with a specific time length, wherein the timing data set indicates the specific signal type and the specific time length. The control unit may be configured to control operations of the receiving circuit and the transmitting circuit.

Abstract: A method for dynamically adjusting a root clock frequency of a logic system design on an emulation system comprises: identifying a plurality of signal paths from one of a plurality of signal inputs of the logic system design to one of a plurality of signal outputs of the logic system design, each of the plurality of signal paths having a signal propagation delay; determining a state of an input signal to a target signal input in a current root clock cycle; determining a target signal path based on the state of the target signal input in the current root clock cycle and one or more logic devices along each signal path associated with the target signal input; and determining the root clock frequency based on a longest signal propagation delay of the signal propagation delays of the plurality of signal paths excluding the target signal path.

Abstract: A system on chip includes: a functional circuit configured to perform a processing operation by receiving a supply voltage; a droop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a droop of the supply voltage has occurred; a clock generation circuit configured to output a first clock signal having a first frequency; and a clock modulation circuit configured to receive the detection signal and the first clock signal, and provide a system clock signal to the functional circuit.

Abstract: There is provided a computer-implemented method, device and system for automatically configuring a computer device located at a particular location of an entity having an associated local network. The method, system and device further comprises: detecting from another computer device metadata characterizing the particular location; determining from the metadata whether the computer device requires configuration and if so, performing configuration steps of: automatically determining a device type for the computer device based on one or more connected peripheral devices, the device type defining a role of the computer device within the particular location; sending metadata comprising the particular location and the device type to a central server for requesting configuration of the computer device and in response, receiving configuration information for the computer device.

Abstract: An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

Abstract: Enhanced resolution for a real-time clock is implemented, which includes a real-time clock configured to operate at a first time resolution, at least one processing unit configured to operate at a second time resolution, wherein the second time resolution has a higher frequency than the first time resolution, a memory for storing data at a location including data from the real-time clock and the at least one processing unit, an interrupt configured to load information into the memory at the location using the at least one processing unit, the interrupt further configured to operate at a frequency associated with the second time resolution, a timing service configured to read information from the memory at the location, the timing service configured to operate at the second time resolution, and a calibration module configured to re-calibrate the real-time clock.

Abstract: According to one embodiment, an automatic transfer switch (ATS) module for an electronic rack includes a container and four pairs of relays that are disposed within the container, each pair having a first relay connected in series with a second relay. A first two pairs of relays are arranged to connect to a first power source and are arranged to connect to a power supply unit, and a second two pairs of relays are arranged to connect to a second power source and are arranged to connect to the power supply unit. The four pairs of relays are arranged in one of several open-closed configurations, such that in a first open-closed configuration the first source connects to the power supply unit through a first two pairs of relays and in a second open-closed configuration the second source connects to the power supply unit through a second two pairs of relays.

Abstract: A communication device for connection with a power source and a host device is provided. The communication device comprises a device controller and a converter circuit. The device controller is adapted for data communication with the host device and the converter circuit is configured to provide a virtual device ground at least to the device controller, so as to compensate a ground potential difference between the host device and the communication device.

Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Abstract: An information processing apparatus which is capable of properly supplying power to an image processing unit and an image output unit from respective different power supplies without using a control instruction. The image processing unit obtains data from an external apparatus. A type of the obtained data is determined, and supply of power to the image processing unit and the image output unit is controlled based on the determined type of the data.

Abstract: In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Abstract: The present disclosure provides a method for syncing data of a computing task across a plurality of groups of computing nodes, each group comprising a set of computing nodes A-D, a set of intra-group interconnects that communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C, and a set of inter-group interconnects that communicatively couple a computing node A of a first group of the plurality of groups with a computing node A of a second group neighboring the first group, a computing node B of the first group with a computing node B of the second group, a computing node C of the first group with the computing node C of the second group, and a computing node D of the first group with a computing node D of the second group, the method comprising: syncing across a first dimension of computing nodes using a first set of ring connections, wherein the first set of ring connections are formed using inter-group and intra-group interconnects that communica