Abstract: A method for determining a clock drift comprises determining a drift of a clock relative to a reference clock based on two signals from the reference clock and a further signal. The method can be used for time synchronization and is suitable for implementation on resource-constrained devices. An anchor point implementing the method and a real-time locating system comprising such an anchor point are also disclosed.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for identifying, during a particular boot of an information handling system, basic input/output system (BIOS)-level events, each BIOS-level event associated with a different BIOS log event source; for each BIOS-level event: creating, by a respective driver computing module associated with the BIOS-level event, event data for the BIOS-level event; calling, by the respective driver computing module associated with the BIOS-level event, a dispatcher protocol to provide the event data associated with the respective driver computing module to a dispatcher computing module; placing, by the dispatcher computing module, each of the event data in a temporary data store, wherein each of the event data is unaltered; and creating, by the dispatcher computing module, a database log of the event data, including aggregating each of the event data to generate a sequence of events related to the particular boot of the IHS.

Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.

Abstract: A system and method for serializing output includes shift registers that sample a deserialized input signal at a relatively slow clock speed. Data latency between the input and output signals is controllable to a higher granularity than the input signal with bit positions corresponding to the high-speed input signal. A predictive learning algorithm receives data latency values from the input signal and corresponding data latency values from the output signal to correct and control output latency, potentially within one high speed clock cycle.

Abstract: The present disclosure discloses a rapid frequency searching method and apparatus for a data processing device, and a data processing device.

Abstract: An electronic device includes a processor, a battery, a charging circuit, a controller, and an arithmetic logic unit. The processor is capable of operating at a preset frequency or a low frequency. The charging circuit is electrically connected to an external power supply and a battery and transmits a disconnection signal and to be powered by the battery when the external power supply and the charging circuit are changed from a connected state to a disconnected state. The controller is configured to transmit a first control signal when the external power supply and the charging circuit are changed from the connected state to the disconnected state. The arithmetic logic unit is configured to transmit a frequency reduction signal to the processor according to the disconnection signal and the first control signal, so that the processor reduces the preset frequency to the low frequency and operates at the low frequency.

Abstract: A blade server with an apparatus for configuring the blade server is disclosed. the blade server includes at least one data processor and the data processor is configured to determine presence of a response file at a remote management module, upon deployment of the blade server, in response to the response file being present, receive the response file from the remote management module, and retrieve an ISO of a desired operating system for the blade server in accordance with data stored in the response file, in order to install the desired operating system for the blade server.

Abstract: A system, method and computer program product for operating a low-voltage Internet-of-Things sensor device. The method includes sensing of the temperature dependence at each voltage condition in addition to the actual temperature and voltage. A programmed machine learning model uses the information to decide when it is appropriate to test the device functionality and use the results of different tests to determine when the system should run synchronously or asynchronously through a machine learning predictive algorithm. Based on said one or more sensed operating conditions, the system uses the model to detect a mode of operation of said IoT device indicating IoT device meets an expected level of performance, or a mode indicating said IoT device is not operating according to the expected level of performance. Based on the detected operating condition, the IoT device automatically adapts its operation to ensure a desired level of IoT sensor device performance.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: There is described an upstream device for translating clock domain for non-synchronized sensors comprising a communication component, a memory component, and a processor. The communication component detects a report received from a sensor that includes a beacon receive time in a sensor clock domain and a current report transmit time in the sensor clock domain. The memory component provides a previous report receive time in the aggregator clock domain and a previous report transmit time in the sensor clock domain. The processor identifies a current report receive time in an aggregator clock domain based on the report detected by the communication component. The processor also determines a beacon receive time in the aggregator clock domain based, at least in part, on the beacon receive time in the sensor clock domain, the current report transmit time, the current report receive time, the previous report receive time, the previous report transmit time.

Abstract: A power consumption optimization system includes a virtual machine (VM) provisioned on a host, a memory, a server, and a processor in communication with the memory. The processor causes the server to store a power consumption profile of the VM. The VM runs at a processor frequency state. Additionally, the processor causes the server to receive a request to lower a processor frequency for the VM from an original processor frequency state to a reduced processor frequency state. The request has request criteria indicating a time duration associated with the request. The server validates the request criteria and a requirement of another tenant on the host. Responsive to validating the request criteria and the requirement the other tenant on the host, the server confirms the request to lower the processor frequency. Additionally, the server lowers the processor frequency to the reduced processor frequency state during the time duration.

Abstract: Techniques and mechanisms for providing redundancy with multiple batteries of a backup power system. In an embodiment, switch circuits are each coupled between a power bus and a different respective one of the multiple batteries. Respective nodes of the switch circuits are each to couple to a different respective power sink, wherein power delivery to the power sinks is monitored. Based on the monitoring, the switch circuits are configured for a first battery to serve a substitute for a second battery. Configuring the switch circuits includes electrically decoupling the second battery from a first node, and electrically coupling the first battery to deliver power via both a power bus and the first node. In another embodiment, multiple backup units each include a respective battery and switch circuit, wherein respective controllers of the backup units intermittently communicate monitoring information via a data bus.

Abstract: Systems and methods for improving idle time estimation by a process scheduler are disclosed. An example method comprises calculating, by a process scheduler operating in a kernel space of a computing system, an estimated idle time for a processing core, responsive to detecting a transition of the processing core from an idle state to an active state, recording, an actual idle time of the processing core, and making the estimated idle time and the actual idle time available to a user space process.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: A mobile terminal, including a clock generator, a first frequency conversion circuit, a first module, a second frequency conversion circuit, and a second module. The first frequency conversion circuit performs frequency conversion on a clock signal generated by the clock generator, to obtain a first clock signal, and outputs the first clock signal to the first module. The second frequency conversion circuit performs frequency conversion on the clock signal generated by the clock generator, to obtain a second clock signal, and outputs the second clock signal to the second module. The mobile terminal has an improved anti-electromagnetic interference capability.

Abstract: A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

Abstract: A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A real time clock device for a vehicle may include: a register set provided with a first register, in which second time information is stored, and configured to store Real Time Clock (RTC) data including the time or date; and a data compensation circuit to block an input of a 1 second (1 s) tick to the first register and compensate for a delay time according to the block of the input of the 1 s tick to the first register by an RTC lock signal during a process of transmitting the RTC data to an external device or receiving setting data for the RTC data from the external device.