Abstract: Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: The present disclosure provides a method for syncing data of a computing task across a plurality of groups of computing nodes, each group comprising a set of computing nodes A-D, a set of intra-group interconnects that communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C, and a set of inter-group interconnects that communicatively couple a computing node A of a first group of the plurality of groups with a computing node A of a second group neighboring the first group, a computing node B of the first group with a computing node B of the second group, a computing node C of the first group with the computing node C of the second group, and a computing node D of the first group with a computing node D of the second group, the method comprising: syncing across a first dimension of computing nodes using a first set of ring connections, wherein the first set of ring connections are formed using inter-group and intra-group interconnects that communica

Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

Abstract: A system comprises a power-over-ethernet (POE) network switch; an intelligent power distribution hub and gateway (IPDHG) configured to communicate with the POE network switch; a rechargeable battery configured to be recharged by the POE network switch; and one or more low duty cycle devices configured to communicate with the IPDHG, wherein the one or more low duty cycle devices are charged by the rechargeable battery.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A system can receive, in association with a user account, an operating system image that is encrypted with a private key, a manifest generated from a first instance of a manifest generator tool that is configured to identify system provisioning artifacts that is encrypted with the private key, and a public key. The system can install the operating system image on a computing device. The system can generate, with a second instance of the manifest generator tool, a first identification of system provisioning artifacts from the installing of the operating system image.

Abstract: An improved method and system for controlling the powering-on of an electronic device when initially the internal temperature is below a safe threshold. The method and system can preheat the electronic device until it is at a safe temperature in which to safely power-on the electronic device. Alternatively or in addition, the method and system can alert a user if the temperature is below a threshold and proceed to power-on when the temperature is above the threshold.

Abstract: Enhanced resolution for a real-time clock is implemented, which includes a real-time clock configured to operate at a first time resolution, at least one processing unit configured to operate at a second time resolution, wherein the second time resolution has a higher frequency than the first time resolution, a memory for storing data at a location including data from the real-time clock and the at least one processing unit, an interrupt configured to load information into the memory at the location using the at least one processing unit, the interrupt further configured to operate at a frequency associated with the second time resolution, a timing service configured to read information from the memory at the location, the timing service configured to operate at the second time resolution, and a calibration module configured to re-calibrate the real-time clock.

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

Abstract: One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: The present disclosure relates to systems and methods for elastic delivery, processing, and storage for wearable devices based on system resources. For example, a wearable apparatus may have at least one battery; at least one sensor configured to measure at least one property associated with a user of the wearable apparatus; at least one memory storing measurements from the at least one sensor and instructions; at least one transmitter configured to send data to a device remote from the wearable apparatus; and at least one processor configured to execute the instructions to: receive, from the at least one battery, an indicator of a charge; and based on the received indicator, sending a command to the at least one sensor to operate in a low-power mode or a high-power mode, the low-power mode having. a lower sampling rate than the high-power mode.

Abstract: This application relates to monitoring of electronic devices (100) and in particular to methods and apparatus for the detection and recording of an electrical overstress applied to a connector (101, 102) of the device. The apparatus describes an integrated circuit (103, 105) of the host device having a first set of one or more circuit contacts (201, 203, 204, 205) for connection to a connector (101) of a host electronic device. The circuit has an electrical overstress monitor (106, 106a) for detecting and recording an electrical overstress comprising a voltage exceeding a predetermined parameter applied to at least one of said first set of circuit contacts. The electrical overstress monitor (106) may have an overvoltage detector (205) and may have a memory (206) for recording the occurrence of an overvoltage and/or a communication module (207) for communicating with other components of the host device in the event of an electrical overstress.

Abstract: A semiconductor device includes a processor unit, a memory storing a boot program, a reset controller and an address check unit. The reset controller controls a reset for the processor unit based on a reset request and outputs a boot address for the boot program to be executed after reset release to the processor unit. The address check unit performs a tampering check for the boot address output from the reset controller and outputs a boot address error signal based on a tampering check result.

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

Abstract: A method is disclosed for operating an electronic data processing system (10) operable under an operating system. The electronic data processing system has a boot system (13) for selectively loading an operating system from one of a plurality of storage media (12, 30). The boot system is accessible to an external user after the user executes an identification protocol with the boot system. The identification protocol is a challenge-response protocol based on a challenge generated by the boot system. More particularly, the challenge is randomly generated by the boot system and communicated to the user in an outgoing message and the user generates a response to the challenge as an incoming message to the boot system. A specific application is related to an electronic data processing system, and to a weighing scale (1), where the authentication system includes the electronic data processing system.

Abstract: A system for synchronization of multiple clocks in a vehicle network includes a processor that is programmed to synchronize a time follower clock to a primary grand leader clock. The primary grand leader clock is monitored and the time follower clock is synchronized to a standby grand leader clock upon a failure of the primary grand leader clock. The time follower clock is synchronized to the primary grand leader clock if a new ignition cycle has occurred between a failure of the primary grand leader clock and a recovery after failure of the primary grand leader clock. The time follower clock continues to be synchronized to the standby grand leader clock if a new ignition cycle has not occurred between the failure of the primary grand leader clock and the recovery after failure of the primary grand leader clock.