Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: The present disclosure provides a signal transmission method and a signal transmission device, which are applied to a digital circuit including a plurality of circuit modules connected in series, and each circuit module is configured to perform corresponding operation processing based on a first clock signal provided by a first clock. The method includes: under driving of a second clock signal provided by a second clock, transmitting a first signal output by a current circuit module to a target circuit module in response to reception of the first signal, the first signal is a signal output by the current circuit module when operating based on the first clock signal, transmission of the first signal is completed within a current clock cycle of the first clock, and a clock rate of the second clock is greater than that of the first clock.

Abstract: Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.

Abstract: In a time synchronization method, after clock board times between service boards are synchronized, a service board obtains a CPU time and the clock board time of the service board according to a preset periodicity, and makes a record. When performing CPU time synchronization between the service boards, the service board obtains a current CPU time of the service board, calculates a synchronization time of the CPU based on the current CPU time, a last recorded CPU time and clock board time, and adjusts the CPU time of the service board to the synchronization time. After the clock board times between the service boards that need to implement CPU high-precision time synchronization are synchronized by using a high-precision time synchronization protocol, the CPU time of each service board is adjusted to a corresponding synchronization time.

Abstract: Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

Abstract: Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

Abstract: An integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring. The wire interconnect including a wire to transmit clock wake signals around the ring transport in advance of data signaling representing a data packet. Each node is to switch from a clock gated state to a clocked state responsive to receiving a clock wake signal. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes. The sleep controller is to configure the select node into a clock suppression state for a specified duration responsive to identifying an idle condition on the ring transport via monitoring of the wire. While in the clock suppression state the node suppresses further transmission of any clock wake signals received at the select node.

Abstract: Example embodiments involve a standby mode of a playback device. An example implementation involves a first playback device receiving, while an audio processing component of the first playback device is in standby, a first packet over a network. The audio processing component consumes relatively less power in standby compared with not operating in standby. In response to receiving the first packet, the first playback device exits standby, and enters a non-standby mode. Entering the non-standby mode enables the audio processing component of the first playback device. The first playback device also broadcasts over the network a second packet comprising a payload that is associated with a destination address. After receiving the first packet, the first playback device forwards packets to a second playback device. Once the first playback device is no longer forwarding the packets, the first playback device enters standby.

Abstract: Apparatuses and methods for preventing accidental-shutdown in a robot-assisted surgical device are disclosed. An exemplary control apparatus includes an on/off key configured to trigger a start action or a shutdown action, an on/off control module configured to detect the shutdown action of the on/off key and obtain a shutdown intention through man-machine interaction, and an on/off hardware circuit configured to detect the start action and send a signal to a power supply. The on/off hardware circuit is configured to detect the shutdown action of the on/off key and a shutdown control signal sent by the on/off control module and send a signal to cut off the power supply. The control apparatus can reduce the probability of accidental shutdown caused by system software and hardware failure or man-made mis-operation and improve the operating reliability of the robot-assisted surgical device without significantly increasing cost.

Abstract: A connector controller controls a connector with a power pin, a communication pin, and a ground pin. The connector detects the voltage at the communication pin at least twice to generate first and second voltages respectively. A bus power is supplied at the power pin. The first voltage is detected when a bus current to/from the bus power is about zero. The connector controller controls the bus power in response to a difference between the first and second voltage.

Abstract: A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.

Abstract: A processor may identify that an external power source has begun powering a computing device. The processor may identify computational data in a volatile memory of the computing device. The processor may determine that the external power source does not have sufficient energy capacity to provide the computing device enough power to process the computational data at a first I/O throttling rate. The processor may increase the first I/O throttling rate to a second I/O throttling rate. The second I/O throttling rate may allow the computational data to be processed by the computing device with the energy capacity of the external power source.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: Software-defined fail-safe power draw control is provided for rack power distribution units (PDUs). A PDU power manager can be used to map devices to a PDU and its sockets. The PDU power manager can also identify the power rating of the PDU and its sockets. With this information, the PDU power manager can generate and apply priority-based and dynamic power caps to the devices connected to the PDU. In this way, the PDU power manager can ensure that the power ratings of the PDU and of each of its sockets are not exceeded while ensuring that power delivery is prioritized based on the workloads that the devices may experience.

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

Abstract: A power consumption optimization system includes a virtual machine (VM) provisioned on a host, a memory, a server, and a processor in communication with the memory. The processor causes the server to store a power consumption profile of the VM. The VM runs at a processor frequency state. Additionally, the processor causes the server to receive a request to lower a processor frequency for the VM from an original processor frequency state to a reduced processor frequency state. The request has request criteria indicating a time duration associated with the request. The server validates the request criteria and a requirement of another tenant on the host. Responsive to validating the request criteria and the requirement the other tenant on the host, the server confirms the request to lower the processor frequency. Additionally, the server lowers the processor frequency to the reduced processor frequency state during the time duration.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Abstract: A brain-computer interface device includes a plurality of pre-amplifiers are configured to amplify physiological signals corresponding to channels to output amplified signals; a multiplexer is configured to output, according to a control signal and a clock signal, the amplified signals; an analog-to-digital converter is configured to convert, according to the clock signal including clocks, the output of the multiplexer into a digital signal including a plurality of digital values corresponding to the clocks, wherein each of the digital values includes bit values; a memory is configured to store the digital signal; and a processor s configured to: add a header corresponding to one channel to each of the digital values according to the clock signal; and delete bit values of higher bits of each of the digital values corresponding to the same channel that are the same as those of a previous digital value, to output a compressed signal.

Abstract: To acquire maintenance information easily from packed electronic equipment without unpacking. An AR display device includes: an information projection unit that performs display on the basis of augmented reality; a wireless power supply unit that performs wireless power supply to packed electronic equipment; a wireless power supply control unit that controls directivity and distance of the wireless power supply unit upon performing wireless power supply to the packed electronic equipment, so that a packing box of the packed electronic equipment is displayed on the information projection unit; a wireless communication unit that performs wireless communication with the packed electronic equipment to which the wireless power supply is performed; and a control unit that displays maintenance information received from the packed electronic equipment on the information projection unit.