Patents Examined by Pho M. Luu
  • Patent number: 11144248
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include memory cells for storing data, page buffers coupled to the memory cells, the page buffers including first latches for temporarily storing original data during a program operation and second latches for storing verification data during a verify operation, and a command execution component for controlling the page buffers, in response to a normal command signal, a suspend command signal, or a resume command signal, to store the original data and the verification data in the first and second latches in response to the normal command signal, to provide the verification data to the first latches in response to the suspend command signal, and to transfer the verification data from the first latches to the second latches in response to the resume command signal.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11145342
    Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Redaelli
  • Patent number: 11139010
    Abstract: Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
  • Patent number: 11133045
    Abstract: A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz
  • Patent number: 11127861
    Abstract: An embodiment includes an apparatus comprising: a thin film transistor (TFT) comprising: source and drain contacts; first and second gate contacts: a semiconductor material, comprising a channel, between the first and second gate contacts; and a first dielectric layer, between the first and second gate contacts, to fix charged particles. Other embodiments are described herein.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventor: Abhishek A. Sharma
  • Patent number: 11121318
    Abstract: RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-? switching layer disposed on the bottom electrode, and a top electrode disposed on the high-? switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dexin Kong, Kangguo Cheng, Juntao Li, Zheng Xu
  • Patent number: 11122683
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 14, 2021
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 11114146
    Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Eric Raymond Evarts, Virat Vasav Mehta, Bahman Hekmatshoartabari
  • Patent number: 11114158
    Abstract: Systems and methods for reducing column switch resistance error RRAM-based crossbar array circuits are disclosed. An example crossbar array circuit includes: a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire; a column switch having a column switch input and a column switch output, connected to the cross-point device; an Op-amp device having a non-inverting input, an inverting input, and an Op-amp output; a three-terminal switch having a first terminal, a second terminal, and a third terminal. The three-terminal switch is connected to the inverting input and is configured to switch between the column switch input and the column switch output; a load resistor is connected with the column switch output and the Op-amp output.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 7, 2021
    Assignee: TetraMem Inc.
    Inventor: Ning Ge
  • Patent number: 11107531
    Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 31, 2021
    Inventor: Hyungjin Kim
  • Patent number: 11101004
    Abstract: A memory device and a reading method thereof are provided. During a second reading period, a second bit line voltage is provided to a bit line having a read finished memory cell. Thus, a voltage difference between a bit line voltage and a pass voltage of memory cells on unselected word lines is reduced. A data value stored in the memory cells on a selected word line is determined according to whether the memory cells on the selected word line enter a preset state during a first reading period and the second reading period.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 24, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Ya-Jui Lee
  • Patent number: 11100960
    Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Dong Hyun Kim, Yo Han Jeong
  • Patent number: 11101002
    Abstract: A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
  • Patent number: 11094703
    Abstract: 3D memory devices with an etch-resistant layer and methods for forming the same are disclosed. A memory device includes a substrate and a memory stack disposed on the substrate. The memory stack includes a plurality of interleaved conductor layers and dielectric layers. The memory device also includes a plurality of memory strings each extending vertically through the memory stack and including a semiconductor plug at a bottom portion of the memory string. The semiconductor plug is in contact with the substrate and includes a top portion doped with an etch-resistant material.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: August 17, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Haifeng Guo, Xiaojin Wang, Chengxing Yu, Lin Lai
  • Patent number: 11087813
    Abstract: A control circuit capable of generating a reliable reference potential while suppressing increase in power consumption and cost. A control circuit causes write processing to be performed individually for a first reference element set to a first resistance state in generating a reference potential used for reading data from a memory element, and a second reference element different from the first reference element, the second reference element being set to a second resistance state different from the first resistance state in generating the reference potential.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 10, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Tezuka
  • Patent number: 11081181
    Abstract: A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. A flash memory that can reliably seek stability of threshold distribution of memory is provided.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 3, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Sho Okabe
  • Patent number: 11081595
    Abstract: A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 3, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Lin Sung, Pei-Ying Du, Hang-Ting Lue
  • Patent number: 11081186
    Abstract: Provided are a non-volatile memory device and an erasing method thereof.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Lee, Young-sik Rho, Il-han Park
  • Patent number: 11075207
    Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi
  • Patent number: 11074966
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 27, 2021
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao