Abstract: A memory system that splits a data width (W) into N separate memories each of narrower width W/N is described. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. A fault on the WE signal to any of the N memories results in its stored write detection bit being different from the write detection bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the write detection bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.

Abstract: Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Abstract: A semiconductor memory includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier including a first latch circuit, a first hookup circuit, a second latch circuit, a first wiring, and a first pre-charge circuit. The sense amplifier is in a first circuit area. The first hookup circuit is in a second circuit area and configured to control connection between the bit line and the sense amplifier. The first wiring is connected between the first latch circuit and the second latch circuit. The first pre-charge circuit includes a first transistor in a third circuit area between the first circuit area and the second circuit area. The first transistor has a first end connected to the first wiring at a first position in the third circuit area and a second end connectable to a terminal supplied with one of a pre-charge voltage and a ground voltage.

Abstract: A memory system may store temperature exception tracking in a temperature log, which may be separate from data to which the temperature information corresponds. A memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

Abstract: A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.

Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert. Any one of the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit may comprises an operational amplifier or a current conveyor.

Abstract: A Content Addressable Memory (CAM) array includes a first and a second cell structure sharing a cell boundary. The first cell structure includes a first storage circuit and a first comparator circuit, the first comparator circuit includes a first transistor having a gate, a drain, and a source. The second cell structure includes a second storage circuit and a second comparator circuit, the second comparator circuit includes a second transistor having a gate, a drain, and a source. The CAM array further includes a first shared source contact landing on the source of the first transistor and the source of the second transistor. The first shared source contact connects the source of the first transistor to the source of the second transistor. And the first shared source contact extends across the shared cell boundary from the first cell structure to the second cell structure.

Abstract: A voltage generation circuit includes a first input terminal at a power supply voltage, a second input terminal at a reference voltage, an output terminal, a resistor circuit, and a capacitor circuit. The resistor circuit includes resistors connected in series between the first and second input terminals and switching elements connected between the output terminal and a respective one of a plurality of nodes. The capacitor circuit includes a plurality of capacitors, each of which has a first terminal to which a first voltage or a second voltage is applicable and a second terminal connected to the output terminal. The first voltage or the second voltage is selectively applied to the first terminals of the capacitors in accordance with a target value of an output voltage.

Abstract: A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Abstract: A semiconductor structure includes a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: A laminated semiconductor which enables curbing of manufacturing cost; a wafer laminate; a method for manufacturing the laminated semiconductor; an assistance device; and a program. This laminated semiconductor formed by laminating a plurality of chips is provided with a logic chip; and a memory part that is stacked on the logic chip and has at least one memory chip communicable with the logic chip. The memory chip has at least two memory bodies that have memory circuits and that are arranged side by side in a direction intersecting the stacking direction; and a connection part which is provided with a prescribed width between the memory bodies and which connects the memory bodies arranged side by side.

Abstract: A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.

Abstract: A failbit counting method includes controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format. Each of the one or more verification bits is a fail bit or a pass bit. The count result in unary format is stored in the counter. The method further includes controlling the counter to transcode the count result stored in the counter from unary format to binary format.

Abstract: The present invention provides an efficient quantum memory for storing a quantum state of light, such as a photon, for a temporary period of time in a fibre-integrated optical cavity and then recall the quantum state of light and quantum information at a later time with a high probability of success. The present invention uses a nonlinear optical switching mechanism to modify at least one property of the quantum light, or cavity, to trap the quantum light in the optical cavity. Subsequent application of the nonlinear optical switching mechanism switches at least one property of the stored quantum light, or cavity, to release the quantum light from the optical cavity. The present invention also provides quasi-deterministic single-photon generation by temporal multiplexing of a photon pair source integrated within the cavity.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Disclosed are a memristor element, a synapse element and a neuromorphic processor including the same. The memristor element includes a free layer including a domain wall; and a fixed layer including a material of which a magnetization direction is fixed, wherein a position of the domain wall in the free layer is changeable based on a spin orbit torque (SOT) generated by a current introduced from an outside, and wherein a resistance value, measured through both ends of the fixed layer, is based on the position of the domain wall and on a Hall voltage.

Abstract: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.

Abstract: A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.

Abstract: A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.