Patents Examined by Pho M. Luu
  • Patent number: 11514981
    Abstract: The method includes setting conductances for corresponding non-volatile memory (NVM) devices of a cross-bar array to zero. The method further includes determining a plurality of pulse-widths for the corresponding plurality of NVM devices based on a corresponding plurality of programming errors. Additionally, the method includes programming the NVM devices using the determined pulse-widths. Also, the method includes measuring actual conductances for the corresponding NVM devices. Further, the method includes adjusting scaling factors for the corresponding NVM devices based on the actual conductances and the corresponding programming errors. Additionally, the method includes programming the corresponding NVM devices based on the determined pulse-widths and the scaling factors.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Stefano Ambrogio, Pritish Narayanan
  • Patent number: 11515871
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 29, 2022
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11514955
    Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Matthew David Rowley
  • Patent number: 11508899
    Abstract: A foil transducer for a valve, including at least one firmly arranged holding part, at least one displaceable force transmission part, an electroactive foil composite structure and at least two electrodes. The electroactive foil composite structure has an actuating direction in which the electroactive foil composite structure is extended on actuation. The actuating direction lies in a plane spanned by the electroactive foil composite structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 22, 2022
    Assignee: Buerkert Werke GmbH & Co. KG
    Inventor: Micah Hodgins
  • Patent number: 11504743
    Abstract: A flexible tactile actuator includes a tactile transmitter configured to be flexible and including magnetic particles capable of being polarized in response to an external magnetic field and a matrix layer including the magnetic particles, a magnetic field generator disposed below the tactile transmitter and configured to generate a magnetic field in the tactile transmitter, and an elastic member provided in a shape of a film, having at least a portion in surface contact with the magnetic field generator, and attached to be in surface contact with one of a top surface and a bottom surface of the tactile transmitter.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 22, 2022
    Assignee: CK MATERIALS LAB CO., LTD.
    Inventors: Hyeong Jun Kim, Myung Sun Park, Jong Hun Lee, Ji Goo Kang, Nam Seok Kim
  • Patent number: 11508448
    Abstract: A memory system including a memory device suitable for performing, in stages, a program loop including a program operation and a program verification operation on each page within a memory block selected among a plurality of memory blocks, updating a maximum number of program loops for the selected memory block by comparing a number of program loops on each page, which are performed until the program verification operation is processed as a pass on the page, with a current maximum number of program loops for the selected memory block, and storing the updated maximum number of program loops for the selected memory block as program pass information of the selected memory block; and a controller suitable for managing the selected memory block as a bad block based on the program pass information of the selected memory block.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Won Jin Jung
  • Patent number: 11508415
    Abstract: A semiconductor memory package structure includes at least one semiconductor die and a lead group. The at least one semiconductor die includes a chip enable terminal. The lead group is configured to electrically connect the chip enable terminal to an external circuit board and includes a first pin and a second pin coupled to the chip enable terminal. The at least one semiconductor die and the lead group are formed as an integral entity using an insulating material.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 22, 2022
    Assignee: Transcend Information, Inc.
    Inventors: Bing-Lian Lin, Chao-Wei Ko
  • Patent number: 11501837
    Abstract: A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 15, 2022
    Assignee: SanDisk Technologies LLC
    Inventor: Abhijith Prakash
  • Patent number: 11502246
    Abstract: A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.
    Type: Grant
    Filed: May 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Shigeki Takahashi
  • Patent number: 11488674
    Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation and a read operation on the memory cell array. The control logic is configured to control an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform an SLC program operation on memory cells included in a selected page among the plurality of memory cells, compares the number of first fail bits counted by performing a normal sensing operation on the selected page and the number of second fail bits counted by performing a multi-sensing operation on the selected page, and corrects at least one evaluation time to be used for a read operation based on a result of the comparison.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11488666
    Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: November 1, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11475958
    Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: October 18, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-yuan Tseng, Swaroop Kaza, Tomer Eliash
  • Patent number: 11468949
    Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 11, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Pitamber Shukla, Giuseppina Puzzilli, Niccolo′ Righetti, Scott A. Stoller, Priya Venkataraman
  • Patent number: 11463063
    Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 4, 2022
    Assignee: Zhuhai Crystal Resonance Technologies Co., Ltd.
    Inventors: Dror Hurwitz, BawChing Perng, Duan Feng
  • Patent number: 11456023
    Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 27, 2022
    Assignee: Kioxia Corporation
    Inventors: Yutaka Shimizu, Satoshi Inoue, Isao Fujisawa, Yumi Takada
  • Patent number: 11456022
    Abstract: The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Srinivas Rajendra, Sayed Mobin, Rehan Ahmed Zakai
  • Patent number: 11450390
    Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 20, 2022
    Assignee: Kioxia Corporation
    Inventors: Fumiya Watanabe, Masaru Koyanagi, Yutaka Shimizu, Yasuhiro Hirashima, Kei Shiraishi, Mikihiko Ito
  • Patent number: 11443968
    Abstract: A substrate treating apparatus and a substrate transporting method. A platform is placed on a first ID block, and a platform is placed on a second ID block. A currently-used carrier platform is provided only on the first ID block. A substrate is transported in both a forward path and a return path between the first ID block and an IF block. The substrate is sent in the return path from the IF block to the second ID block disposed between a coating block and a developing block without being transported from the IF block to the first ID block. Consequently, transportation process in the return path by the coating block disposed between the first ID block and the second ID block is reduced. As a result, an entire throughput of a substrate treating apparatus can be enhanced.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 13, 2022
    Inventor: Joji Kuwahara
  • Patent number: 11443816
    Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, the first digitally-controlled pump voltage level applied to the charge pump is caused to change to a second digitally-controlled pump voltage level.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 11437501
    Abstract: In a technique for inducing local electric field controlled magnetization, despite the absence of magnetic components, there is provided a novel heterostructure, a semiconductor device thereof, or an array of semiconductor devices. The heterostructure includes a semiconductor substrate carrying a plurality of layers forming at least one heterojunction and hosting a two-dimensional electron gas layer when one of the layer of the plurality of layers is bounded to an interacting layer being a chiral or a biological macromolecule assembly.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: September 6, 2022
    Assignees: Yeda Research and Development Co. Ltd., Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.
    Inventors: Yossef Paltiel, Ron Naaman, Karen Michaeli, Eilam Smolinsky