Abstract: A predictive clock controller is provided for modifying the frequency of a clock signal provided to a processing unit based on knowledge of the power usage by the application running on the processing unit during different execution periods. The predictive clock controller counts barrier syncs for the application, so as to determine where the application is in its sync schedule. The predictive clock controller is able to determine from the number of counted syncs, when the application will transition from one execution period to another execution period with different power requirements, and to adjust the clock frequency accordingly.

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases: storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array; reading from said counter the value corresponding to the number of bits having the predetermined logic value; reading the data stored in the array of memory cells by applying a ramp of biasing voltages; counting the number of bits having the predetermined logic value during the data reading phase; stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

Abstract: A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.

Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: A continuous thin film comprises a metal chalcogenide, wherein the metal is selected from the periodic groups 13 or 14 and the chalcogen is: sulphur (S), selenide (Se), or tellurium (Te), and wherein the thin film has a thickness of less than 20 mm. Methods of forming the continuous thin film involve thermally evaporating precursors to form a thin film on the surface of a substrate. In a particular embodiment, molecular beam epitaxy (MBE) is used to grow indium selenide (In2Se3) thin film from two precursors (In2Se3 and Se) and the thin film is used to fabricate a ferroelectric resistive memory device.

Abstract: A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells forming a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input. The SRAM computation architecture is configured to store ternary data and perform local computations on the ternary data.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: A memory cell having a Josephson junction and a magnetic junction situated in a close proximity to the Josephson junction. The two junctions may be vertically integrated. The magnetic junction has at least two magnetic layers with different coercive forces and a non-magnetic layer therebetween, to form a spin valve or pseudo-spin valve. A magnetization direction of a magnetic layer with lower coercive force can be rotated with respect to the larger coercive force magnetic layer(s). Magnetic fields produced by appropriately configured control lines carrying electric current, or spin-polarized current through the magnetic junction, can result in rotation. The magnetic junction influences the Josephson critical current of the Josephson junction, leading to distinct values of critical current which can serve as digital logic states. The so obtained memory cell can be integrated into the large arrays containing a plurality of the cells, to enable the selective READ and WRITE operations.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A magnetic recording array includes a plurality of units. Each unit has a first magnetoresistance effect element, second magnetoresistance effect element, and writing transistor. Each of the first magnetoresistance effect element and the second magnetoresistance effect element has a wiring and a laminate which is laminated on the wiring. The writing transistor is connected to each of the wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element. The wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element are electrically connected in series at the time of writing, and a writing current flows through each of the wirings. A direction of a writing current flowing in the wiring of the first magnetoresistance effect element and a direction of a writing current flowing in the wiring of the second magnetoresistance effect element are opposite to each other.

Abstract: A magnetoresistance memory device includes; first and second switching elements; first and second layer stacks respectively on the first and second switching elements; a first insulator on a side surface of the first layer stack; and a second insulator on a side surface of the second layer stack. Each of the first and second switching elements includes a variable resistance material. Each of the first and second layer stacks includes first and second ferromagnetic layers and an insulating layer between the first and second ferromagnetic layers. A narrowest interval between the first and second insulators is narrower than a narrowest interval between the first and second switching elements.

Abstract: A magnetic device is described. The magnetic device includes a magnetic junction, a spin-orbit interaction (SO) line and a dipole-coupled layer. The magnetic junction includes a free layer. The SO line is adjacent to the free layer, carries a current in-plane and exerts a SO torque on the free layer due to the current passing through the SO line. The free layer being switchable between stable magnetic states using the SO torque. The SO line is between the free layer and the dipole-coupled layer. The dipole-coupled layer is magnetically coupled to the free layer. At least one of the free layer and the dipole-coupled layer has a damping of greater than 0.02.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.