Patents Examined by Pho M. Luu
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Patent number: 11264102Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.Type: GrantFiled: August 31, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Kiichi Tachi, Takashi Hirotani
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Patent number: 11250921Abstract: A programming and verifying method for a multi-level memory cell array includes following steps. In a step (a1), a first row of the multi-level memory cell array is set as a selected row, and A is set as 1. In a step (a2), memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are programmed to the A-th storage state. In a step (a3), if A is not equal to X, 1 is added to X and the step (a2) is performed again. In a step (a4), if A is equal to X, the program cycle is ended. In the step (a2), the first-portion memory cells of the selected row are subjected to plural write actions and plural verification actions until all of the first-portion memory cells reach the A-th storage state.Type: GrantFiled: October 14, 2020Date of Patent: February 15, 2022Assignee: EMEMORY TECHNOLOGY INC.Inventors: Ying-Je Chen, Wei-Ming Ku, Wein-Town Sun
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Patent number: 11249843Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and a period signal generation circuit. The ECS command generation circuit generates an ECS command based on a refresh command. The period signal generation circuit generates a sampling period signal, during a sampling period, based on the ECS command and generates an operation period signal, during an operation period, based on the ECS command. A latch error flag is generated to include information on whether errors exist in codewords during the sampling period, and an ECS operation is performed based on the latch error flag, during the operation period, for memory cells that store an erroneous codeword among the codewords.Type: GrantFiled: June 23, 2020Date of Patent: February 15, 2022Assignee: SK hynix Inc.Inventor: Choung Ki Song
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Patent number: 11244714Abstract: A method of writing to a magnetic random access memory cell includes applying an alternating current signal to the magnetic random access memory cell having a first magnetic orientation, and applying a direct current pulse to the magnetic random access memory cell to change the magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.Type: GrantFiled: February 8, 2021Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Duen-Huei Hou
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Patent number: 11238941Abstract: A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.Type: GrantFiled: August 31, 2020Date of Patent: February 1, 2022Assignee: Kioxia CorporationInventor: Hiroki Date
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Patent number: 11239160Abstract: E-fuses and techniques for fabrication thereof using dielectric zipping are provided. An e-fuse device includes: a first dielectric layer disposed on a substrate; at least one first electrode of the e-fuse device present in the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; vias present in the second dielectric layer, wherein at least one of the vias is present over the at least one first electrode and has a critical dimension CDA?, wherein the vias adjacent to the at least one via having the critical dimension CDA? each have a critical dimension of CDB?, and wherein CDB?>CDA?; a liner disposed in each of the vias; and a metal that serves as a second electrode of the e-fuse device disposed in each of the vias over the liner. A method of operating an e-fuse device is also provided.Type: GrantFiled: June 16, 2020Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Tianji Zhou, Saumya Sharma, Ashim Dutta, Chih-Chao Yang
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Patent number: 11238932Abstract: In a method of operating a nonvolatile memory device, the nonvolatile memory device includes a memory block that includes a plurality of memory cells and is connected to a plurality of wordlines. A data write command is received. Based on the data write command, a first program operation is performed on some wordlines among the plurality of wordlines connected to the memory block. At least one of the some wordlines on which the first program operation is performed is detected as a no-coupled wordline. Without the data write command, a second program operation is performed on an open wordline on which the first program operation is not performed and adjacent to the no-coupled wordline.Type: GrantFiled: June 3, 2020Date of Patent: February 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Seongho Ahn
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Patent number: 11239133Abstract: A semiconductor memory system having a plurality of semiconductor memory modules that are spaced apart from each other by a gap. The system includes a heat dissipation assembly having a thermally conductive base portion configured to transfer heat away from the memory devices. The heat dissipation assembly including at least one cooling unit extending from the base portion. The at least one cooling unit having a wall with an exterior surface and a cavity. The cooling unit is configured to fit in the gap between adjacent memory modules such that a portion of the exterior surface on a first side of the cooling unit is coupled to one of the first memory devices and another portion of the exterior surface on a second side of the cooling unit is coupled to one of the second memory devices across the gap.Type: GrantFiled: April 19, 2021Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Xiaopeng Qu, Shams U. Arifeen
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Patent number: 11232844Abstract: An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.Type: GrantFiled: May 22, 2020Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Amit Berman
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Patent number: 11227658Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.Type: GrantFiled: June 17, 2020Date of Patent: January 18, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Kenichi Arakawa, Sho Okabe
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Patent number: 11222151Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.Type: GrantFiled: July 20, 2020Date of Patent: January 11, 2022Assignee: Mitsubishi Electric CorporationInventors: Katsumi Uryu, Tadaharu Minato, Takahiro Nakatani
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Patent number: 11222705Abstract: A memory device and an operating method thereof are provided. The memory device includes: a plurality of memory strings connected between a bit and source lines, the plurality of memory strings connected to a first select line, a plurality of word lines, and a second select line, which are disposed between the bit line and the source line; a peripheral circuit for programming a selected memory cell included in a selected memory string among the memory strings; and control logic for controlling the peripheral circuit to program the selected memory cell. The control logic controls the peripheral circuit to apply a positive voltage to the bit and source lines, which are connected to an unselected memory string, before a program voltage is applied to a selected word line connected to the selected memory cell, and discharge the word lines and the first and second select lines at different times.Type: GrantFiled: June 12, 2020Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventor: Hee Youl Lee
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Patent number: 11217296Abstract: Methods, systems, and devices for staggered refresh counters for a memory device are described. The memory device may include a set of memory dies each coupled with a common command and address (CA) bus and each including a respective refresh counter. In response to a refresh command received over the CA bus, each memory die may refresh a set of memory cells based on a value output by the respective refresh counter for the memory die. The refresh counters for at least two of the memory dies of the memory device may be offset such that they indicate different values when a refresh command is received over the CA bus, and thus at least two of the memory dies may refresh memory cells in different sections of their respective arrays. Offsets between refresh counters may be based on different fuse settings associated with the different memory dies.Type: GrantFiled: March 27, 2020Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
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Patent number: 11217294Abstract: Methods, systems, and devices for techniques for adjusting current based on operating parameters are described. An apparatus may include an amplifier, a feedback component, and first and second current generators. The amplifier may include an input for receiving a first voltage and an output for outputting a second voltage. The first current generator may be coupled with the output of the amplifier and generate a first current based at least in part on the second voltage. The feedback component may be coupled with the first current generator to modify the first current based at least in part on an operating temperature associated with a memory device. The first current may be proportional to the operating temperature. The second current generator may be coupled with the first current generator to generate a second current based at least in part on the first current modified by the feedback component.Type: GrantFiled: April 17, 2020Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Wei Lu Chu, Dong Pan
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Patent number: 11211391Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction.Type: GrantFiled: March 10, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Patent number: 11211125Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.Type: GrantFiled: November 17, 2020Date of Patent: December 28, 2021Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 11211119Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: GrantFiled: June 11, 2020Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
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Patent number: 11205681Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.Type: GrantFiled: December 1, 2020Date of Patent: December 21, 2021Assignee: Micron Technology, Inc.Inventor: Andrea Redaelli
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Patent number: 11200953Abstract: A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.Type: GrantFiled: February 9, 2021Date of Patent: December 14, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhipeng Dong, Venkatagirish Nagavarapu, Haibo Li
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Patent number: 11195992Abstract: A spin-orbit torque type magnetization rotational element includes; a spin-orbit torque wiring that extends in a first direction; a first ferromagnetic layer that is laminated in a second direction intersecting the spin-orbit torque wiring; and a first nonmagnetic metal layer and a second nonmagnetic metal layer that are connected to the spin-orbit torque wiring at positions flanking the first ferromagnetic layer in the first direction in a plan view from the second direction, wherein the gravity center of the first ferromagnetic layer is positioned on a side closer to the first nonmagnetic metal layer or the second nonmagnetic metal layer than is a reference point located at the center between the first and second nonmagnetic metal layers in the first direction.Type: GrantFiled: January 9, 2019Date of Patent: December 7, 2021Assignee: TDK CORPORATIONInventors: Eiji Komura, Tomoyuki Sasaki
