Abstract: A method of accessing a nonvolatile memory device which includes a memory block where semiconductor layers including word lines are stacked includes receiving a write request for the memory block, determining whether the write request corresponds to one or more leading word lines, programming, in response to the write request determined as corresponding to the leading word lines, memory cells connected thereto in a first program mode, and programming, when the write request is determined as corresponding to a following word line different from the leading word lines, memory cells connected to the following word line in a second program mode. The second program mode is performed with a second program parameter including at least one of a number of program pulses, a number of program verify pulses, a program start voltage, and a program end voltage that is different from a corresponding first parameter of the first program mode.

Abstract: Certain aspects of the present disclosure provide techniques for relate to electronic devices that are configured to implement multi-rank high bandwidth memory (HBM) memory. In one aspect, an electronic device includes a chip that includes an interface circuit. The interface circuit is connected to first exterior pads. The first exterior pads have a first number of first data input/output exterior pads and a second number of clock enable output exterior pads. The first number is a first integer multiple of a number of data signals per channel of high bandwidth memory (HBM), and the second number is a second integer multiple of a number of clock enable signals per channel of the HBM. The second integer multiple is greater than the first integer multiple.

Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: A semiconductor memory device includes at least two transistors, each including a gate that traverses, in a first direction, an active region of a first substrate defined by an isolation layer, and junction regions disposed in the active region on opposite sides of the gate, and coupled to a memory cell array through a bit line; and a plurality of contacts, coupled respectively to the junction regions, that pass through a dielectric layer that covers the transistor. Among the plurality of contacts, a contact coupled to a junction region to which an erase voltage is loaded is disposed at a center portion of the active region in the first direction, and a contact coupled to a junction region to which the erase voltage is not loaded is disposed at an edge portion of the active region in the first direction.

Abstract: A memory system includes: a memory device suitable for storing a data; a controller suitable for controlling an operation of the memory device based on a control signal; and an interface device includes a signal transfer device suitable for transferring the control signal from the controller to the memory device and transferring the data between the memory device and the controller; and a signal control device suitable for controlling an operation of the signal transfer device in response to an interface control signal included in the control signal, wherein the interface control signal includes a blocking command for stopping an operation of the signal transfer device, a correction command for correcting a duty cycle of the control signal, and an unblocking command for resuming the operation in response to the corrected control signal, of the signal transfer device.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Abstract: A semiconductor memory device includes memory cells, a word line, and a controller. The controller is configured to: execute a first program operation in which a first program voltage is applied to the word line; execute a second program operation in which the first program voltage is applied to the word line, when a resumed first verify operation ends; and execute a third program operation in which a second program voltage higher than the first program voltage is applied to the word line, after a resumed second verify operation.

Abstract: A method for reading memory cell, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first a

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

Abstract: A memory device includes a cross-point array of spin-torque transfer MRAM cells. First rail structures laterally extend along a first horizontal direction. Each of the first rail structures includes a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer. Second rail structures laterally extend along a second horizontal direction. Each of the second rail structures includes a second electrically conductive line that overlies the first rail structures. A two-dimensional array of pillar structures is located between a respective one of the first rail structures and a respective one of the second rail structures. Each of the pillar structures includes a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction.

Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include memory cells for storing data, page buffers coupled to the memory cells, the page buffers including first latches for temporarily storing original data during a program operation and second latches for storing verification data during a verify operation, and a command execution component for controlling the page buffers, in response to a normal command signal, a suspend command signal, or a resume command signal, to store the original data and the verification data in the first and second latches in response to the normal command signal, to provide the verification data to the first latches in response to the suspend command signal, and to transfer the verification data from the first latches to the second latches in response to the resume command signal.

Abstract: Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.