Abstract: A substrate treating apparatus and a substrate transporting method. A platform is placed on a first ID block, and a platform is placed on a second ID block. A currently-used carrier platform is provided only on the first ID block. A substrate is transported in both a forward path and a return path between the first ID block and an IF block. The substrate is sent in the return path from the IF block to the second ID block disposed between a coating block and a developing block without being transported from the IF block to the first ID block. Consequently, transportation process in the return path by the coating block disposed between the first ID block and the second ID block is reduced. As a result, an entire throughput of a substrate treating apparatus can be enhanced.

Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, the first digitally-controlled pump voltage level applied to the charge pump is caused to change to a second digitally-controlled pump voltage level.

Abstract: A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil.

Abstract: In a technique for inducing local electric field controlled magnetization, despite the absence of magnetic components, there is provided a novel heterostructure, a semiconductor device thereof, or an array of semiconductor devices. The heterostructure includes a semiconductor substrate carrying a plurality of layers forming at least one heterojunction and hosting a two-dimensional electron gas layer when one of the layer of the plurality of layers is bounded to an interacting layer being a chiral or a biological macromolecule assembly.

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Abstract: An electronic device includes a memory device and a timing controller configured to output control signals, which are generated using a first clock signal, to the memory device, generate first captured data by capturing data, which is output from the memory device, using the first clock signal in response to the control signals, and generate control signals using a second clock signal and output the control signals to the memory device when the first captured data is not valid data.

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Abstract: A memory system includes: a nonvolatile memory and a memory controller. The nonvolatile memory includes: a first memory cell and a second memory cell each configured to store data and coupled in parallel to a bit line, a first word line coupled to the first memory cell, and a second word line coupled to the second memory cell and differing from the first word line. The first and second memory cell face each other between the first word line and the second word line. The memory controller is configured to read first data from the first memory cell, read second data from the second memory cell, and decode data stored in the first memory cell based on the first data and the second data.

Abstract: Methods, systems, and apparatus for simulating a physical system. A Hamiltonian describing the physical system is transformed into a qubit Hamiltonian describing a corresponding system of qubits, the qubit Hamiltonian comprising a transformed kinetic energy operator. The evolution of the system of qubits under the qubit Hamiltonian is simulated, including simulating the evolution of the system of qubits under the transformed kinetic energy operator by applying a fermionic swap network to the system of qubits. The simulated evolution of the system of qubits under the qubit Hamiltonian is used to determine properties of the physical system.

Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: A memory device includes a first ferromagnetic layer, an insulating layer above the first ferromagnetic layer, a second ferromagnetic layer above the insulating layer, a capping layer on an upper surface of the second ferromagnetic layer, and an electrode on an upper surface of the capping layer. The second ferromagnetic layer includes iron atoms. The capping layer includes one or more elements identical to one or more elements in the second ferromagnetic layer. The electrode includes one or more elements identical to one or more of the elements in the capping layer and includes a material having a Vickers hardness higher than a Vickers hardness of an iron atom.

Abstract: A semiconductor device includes two-terminal memory devices characterized by a range of program voltages and a first capacitance, wherein the two-terminal memory devices are coupled in parallel between ground and a first common node, a first capacitor having a second capacitance, coupled between ground and a second common node, a voltage source configured to provide an input voltage lower than the range of program voltages, a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node, a first resistance device coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.

Abstract: Provided is a method of a generating a skyrmion. The method includes a step of preparing a magnetic multilayer system and a step of generating a skyrmion at a temperature of 400° C. or higher by adjusting the magnetic anisotropy value and the magnetization value of the magnetic multilayer system.

Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: An integrated chip includes a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and includes source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and includes source/drain regions disposed on the opposite sides of the floating gate.

Abstract: Systems and methods are provided for specifying safety rules for robotic devices. A computing device can determine information about any actors present within a predetermined area of an environment. The computing device can determine a safety classification for the predetermined area based on the information. The safety classification can include: a low safety classification if the information indicates zero actors are present within the predetermined area, a medium safety classification if the information indicates any actors are present within the predetermined area all are of a predetermined first type, and a high safety classification if the information indicates at least one actor present within the predetermined area is of a predetermined second type. After determining the safety classification for the predetermined area, the computing device can provide a safety rule for operating within the predetermined area to a robotic device operating in the environment.

Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Abstract: A sintering press to sinter electronic components on a substrate comprises a pressing unit comprising a multi-rod cylinder having a front head and a rear head which jointly delimit a compression chamber. In the front head, presser rods parallel and independent of each other are slidingly supported. Each presser rod is coaxial and barycentric to a respective electronic component to be sintered and has a thrust section proportional to the force to be applied to the respective electronic component. In the compression chamber a sealing membrane extends, which is deformed so as to abut against the presser rods for transferring the sintering pressure on each presser rod.

Abstract: An apparatus and method for hybrid software-hardware coherency.