Patents Examined by Phong H Dang
  • Patent number: 9830286
    Abstract: A method and system for permitting a guest to program a message-signaled interrupt-based device is disclosed. A hypervisor of a host detects a request by a guest to map an address range of memory of the guest to a message signaled-interrupt capability table associated with a device. The hypervisor maps the message signaled-interrupt capability table from a message signaled-interrupt capability register of a programmable interrupt controller associated with the host to the address range of memory of the guest. The hypervisor detects an attempt by the guest to program the device with the message-signaled interrupt configuration located in the address range of memory of the guest. The hypervisor programs the device with the message-signaled interrupt configuration specified by the guest in the address range of memory of the guest.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: November 28, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Avi Kivity, Dor Laor
  • Patent number: 9703737
    Abstract: A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventor: Oluf Bagger
  • Patent number: 9690741
    Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: June 27, 2017
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Gopi Krishnamurthy
  • Patent number: 9672185
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
  • Patent number: 9665514
    Abstract: A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: May 30, 2017
    Assignee: ARM Limited
    Inventor: Ramamoorthy Guru Prasadh
  • Patent number: 9658971
    Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 23, 2017
    Assignee: NXP USA, Inc.
    Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
  • Patent number: 9600426
    Abstract: A bus control device includes a plurality of bus masters classified into a plurality of groups according to a priority level, a plurality of group buses each group bus being connected to a corresponding group of bus masters and assigned with a priority level determined according to the priority levels of the corresponding group of bus masters, an upper priority bus that arbitrates a plurality of bus obtaining requests received from the plurality of bus maters via the plurality of group buses, a plurality of masks respectively provided for the plurality of bus masters to mask the bus obtaining request addressed to the corresponding group bus from the corresponding bus master, and a plurality of mask controllers respectively provided for the plurality of group buses to output at least one mask signal that controls operation of at least one corresponding mask connected to the corresponding group bus.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 21, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshikazu Gyobu
  • Patent number: 9588931
    Abstract: Embodiments of the invention are generally directed to communication bridging between devices via multiple bridge elements. An embodiment of an apparatus includes a transmitter element to transmit data, and multiple bridge elements, the bridge elements including a first bridge element to receive data from the transmitter element and a second bridge element to provide data to a receiver. The bridge elements provide for one or more of translation of one or more commands for an operation from the transmitter element, wherein translation of commands includes handling of a command intended for the receiver, and pre-fetching of one or more data for the operation from the receiver.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: March 7, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jason Wong, Lei Ming, Hyuck Jae Lee
  • Patent number: 9575919
    Abstract: In a storage device applying PCIe to a back-end network connection, in order to be capable of allocating bus numbers and making a PCIe switch expanded afterwards usable, it is necessary to once reset all PCIe switches. To dissolve this necessity, PCIe switches of the back-end network of the storage device are connected in series, a range of continuous bus numbers that are managed and stored in bus number management table is allocated for the back-end network connection, and when expanding the PCIe switch, the bus numbers are allocated in ascending order from a minimum value of the allocatable bus numbers to each of a link between the PCIe switches and to a virtual PCI bus within the PCIe switch, and the bus numbers are allocated in descending order from a maximum value of the allocatable bus numbers to the link between the PCIe switch and a drive.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 21, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hirotoshi Akaike, Katsuya Tanaka, Makio Mizuno
  • Patent number: 9542347
    Abstract: A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported peripheral device, processes messages from a first host. A host manager module routes asynchronous communications, including but not limited to HID input reports, from a client to a host via one of a plurality of supported transports via a targeted transport indicated in the communication. The host manager modules routes synchronous communications from a host to a client via a targeted transport selected from a plurality of transports.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventor: James Trethewey
  • Patent number: 9514084
    Abstract: The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer system 100 includes: a transaction monitor 60 for monitoring first transaction states TrC1-TrCn between a CPU 20 and an L2 cache 25, and second transaction states from TrB0 to TrBn between a system bus 10 and the L2 cache 25, between the system bus 10 and a bus master device 30 or between the system bus 10 and bus slave devices 40, 42; and a clock generator 70 able to change the frequency FreqC1-FreqS2 of the clock of the CPU 20, the system bus 10, and the bus slave devices 40, 42 according to the first transaction and second transaction states received from the transaction monitor 60.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
  • Patent number: 9514073
    Abstract: In a method for exchanging data in messages between users of a CAN bus system, the users have their own time bases; a first user functioning as timer transmits a reference message having a specifiable identifier via the bus, which includes a first time information with regard to the time base of the first user; the at least second user, using its time base forms its own second time information as a function of the first time information of the first user in such a way that, from the deviation of the first and the second time information a correction value is ascertained, so that from the first time information of the first user as the timer, the global time for the bus system is yielded.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 6, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Florian Hartwich, Christian Horst
  • Patent number: 9465761
    Abstract: A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an analog electrical signal generator, which generates an analog electrical signal that describes a second physical state of the first device; a hybrid digital state signal generator, which generates a hybrid digital state signal that comprises the analog electrical signal overlaid onto the initial digital electric signal; and a hybrid signal transmitter, which transmits the hybrid digital state signal from the first device to a second device, wherein the second device comprises a hybrid signal receiver/decoder that extracts the analog electrical signal from the hybrid digital state signal.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 11, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Michael Decesaris, James J. Parsonese, Luke D. Remis, Gregory D. Sellman
  • Patent number: 9448953
    Abstract: The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
  • Patent number: 9442877
    Abstract: According to one embodiment, a storage device includes a processing unit and a plurality of storage units. The processing unit includes a processor and a network communication unit. The storage unit includes a processor input/output port connected to the processing unit via a bus, a storage-unit input/output port connected to adjacent storage unit thereto, a memory capable of storing data, and a routing unit configured to perform a transfer process by determining a transfer route of the data to another one of the storage units on the basis of positional information of the storage unit included in the data.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Sasaki, Takahiro Kurita, Atsuhiro Kinoshita
  • Patent number: 9442876
    Abstract: A network interface controller includes a plurality of host interfaces configured to communicate with a plurality of processing nodes, a plurality of network interfaces configured to provide network communication for the processing nodes to a network, and a shared resource configured to provide link based services and stateless offload services for the processing nodes when communicating with the network.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: September 13, 2016
    Assignee: Dell Products, LP
    Inventors: Robert W. Hormuth, Robert L. Winter, Shawn J. Dube, Bradley J. Booth, Geng Lin, Jimmy Pike
  • Patent number: 9436637
    Abstract: A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away from any other node. Each node also has connection paths to at most three other nodes.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: September 6, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sudarshanam Kommanaboyina
  • Patent number: 9411762
    Abstract: A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Mohan Nair
  • Patent number: 9395786
    Abstract: A method for cross-layer power management in a multi-layer system includes determining whether there is a service level violation for an application running on a hardware platform. Power consumption of the hardware platform is controlled in response to the service level violation.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: July 19, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Jeffrey S. Autor, Sanjay Kumar, Parthasarathy Ranganathan
  • Patent number: 9378162
    Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 28, 2016
    Assignee: ARM Limited
    Inventors: Anthony Jebson, Andrew John Turner, Matthew Lucien Evans, Gareth James Evans, Adam James McNeeney