Abstract: A device includes a first input/output (I/O) port for communication with an external processor, a second I/O port for communication with a second device, and an interface adaptor supporting communication through the first and second I/O ports via a protocol having a plurality of layers, including an application layer, a physical layer, and a physical adaptor layer. The application layer processes information according to an application layer format and the physical adaptor layer processes information according to a physical adaptor layer format. The device receives from the external processor through the first I/O port a request in the application layer format that one or more communication conditions be set for a physical layer of the second device, converts the request from the application layer format to the physical adaptor layer format, and sends the converted request in the physical adaptor layer format to the second device through the second I/O port.

Abstract: In some implementations, a display controller controlling a video input of a display device may select a first set of parameter values from multiple sets of parameter values to configure the video input. After receiving a request from a video source, the display controller may initiate link training. After the link training is completed, the display controller may generate a current link score, determine that the current link score is greater than a stored link score, set a value of the stored link score to be the current link score, and store the first set of parameter values. After selecting each set of parameter values from the multiple sets of parameter values, the display controller may configure the video input of the display device based on the set of parameter values from the multiple sets of parameter values that generated the stored (highest) score.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: The present embodiments relate to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit. The interface circuitry may include a daisy chain of feeder circuits and a daisy chain of drain circuits. If desired, the interface circuitry may include multiple daisy chains of feeder circuits and/or multiple daisy chains of drain circuits. These multiple daisy chains of feeder circuits and drains circuits may be coupled in parallel, respectively. In some embodiments, the interface circuitry may include synchronization circuitry that is coupled between the daisy chains of drain circuits and the serial interface circuit. Pipeline register stages between feeder circuits and/or between drain circuits may enable the placement of the feeder circuits and/or the drain circuits spatially close to the processing elements of the array of processing elements.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a peripheral device, and a service processor communicatively coupled to the processor and the peripheral device and configured to perform out-of-band management of the information handling system. The service processor may further configured to communicatively couple to a management controller having executing thereon a virtual service processor, receive a command associated with the peripheral device from the management controller, deliver the command to the peripheral device, receive data from the peripheral device, and communicate the data to the management controller.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: Provided is a vehicle display device such that the responsiveness of communication between a main microcomputer and a sub microcomputer is improved. The vehicle display device is equipped with a main microcomputer that generates information data and a sub microcomputer that generates an image to be displayed on a display element on the basis of the information data. Between the main microcomputer and the sub microcomputer, at least a signal line for data transmission and a signal line for chip select signal transmission are connected so as to allow communication between the main microcomputer and the sub microcomputer. The vehicle display device synchronizes a first timer counter counted by the main microcomputer and a second timer counter counted by the sub microcomputer, in response to the tip select signal transmitted to the sub microcomputer by the main microcomputer.

Abstract: Disclosed are various embodiments for managing paths in a cluster environment. The cluster environment receives a request from a client to access a logical storage volume via a selected one of a plurality of paths defined for the logical storage volume. In response to an access of the logical storage volume via one of the paths, the cluster environment updates a timestamp for the respective path that corresponds to a time of the access via the respective path. Subsequently, the cluster environment determines a remote path defined for the logical storage volume that can be removed based upon comparing a timestamp for the selected path with a timestamp for the remote path.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. The controller controls the operation of the nonvolatile memory. The interface includes first and second input/output units that transmit and receive a signal with respect to a host device. The first and second input/output units are set on the first hierarchy having the same communication function. The interface issues a connection request to the first input/output unit and when the connection request to the first input/output unit is rejected, the interface issues the connection request to the second input/output unit.

Abstract: Methods, systems, and computer program products for using a stored interrupt location to provide fast interrupt register access in hypervisors are presented. A computer-implemented method may include maintaining an area of memory in a hypervisor to track a location of an interrupt vector corresponding to an asserted interrupt in a virtual machine, storing the location of the interrupt vector in the area of memory when responding to the asserted interrupt, and examining the area of memory to determine when an interrupt is present in the virtual machine.

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) sign

Abstract: A method of operating a data transport system on a computing device is disclosed. The method comprises: writing outgoing data in a first memory space on a memory module of a computing device; detecting the outgoing data on the first memory space by a data channel component coupled to the memory module, wherein the first memory space is designated for external data transmission; and generating a transmission signal encoding the outgoing data, via the data channel component, for transmission from the memory module through an inter-device interconnect to an external memory module.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.

Abstract: Method and systems are disclosed for transporting simultaneous video and bus protocols over a single cable. At least some of the illustrative embodiments are systems including a main switch configured to operate in an enhanced mode where the main switch is configured to transfer data from a first data source and a second data source to a cable, operate in a default mode where the main switch is configured to transfer data from the second data source to the cable without transferring data from the first data source; a multipurpose switch configured to operate in a handshake mode where the multipurpose switch transports handshake data between the cable and a digital logic, operate in a data mode where the multipurpose switch transports bus data between the cable and the second data source; and the digital logic programed to enable modes of operation of the multipurpose switch and the main switch.

Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

Abstract: A communication load determining apparatus is used for a communication system which includes a plurality of communication devices performing communication via a common bus. The communication system operates in accordance with a communication protocol that defines which a priority order is set to each of the frames transmitted from the communication devices and which a frame having a lower priority has a longer transmission latency before being transmitted to the bus. In the communication load determining apparatus, a low-priority frame having a lower priority than other frames to the bus is transmitted, and a transmission latency of the low-priority frame is measured. The communication load determining apparatus determines whether or not abnormality has occurred in a communication load in the bus on the basis of the measured transmission latency to produce a determination result. The produced determination result is stored.

Abstract: A device includes a power control analog subsystem of a universal serial bus-power delivery (USB-PD) compatible power supply device. The power control analog subsystem includes a programmable current sensing circuit and a current sense resistor coupled to the power control analog subsystem. The power control analog subsystem is configured to concurrently compare a current flow through the current sense resistor with at least three different reference values, e.g., compare a sensed voltage with at least three different reference voltages.

Abstract: A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.