Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

Abstract: There are provided a universal asynchronous receiver/transmitter (UART) unit, and a memory controller and a memory system, which have the UART unit. A UART unit includes: a WORD table to store text information and a plurality of word codes corresponding to the text information, and to output a first word code corresponding to first text information when the first text information is received by the WORD table, wherein the text information includes a plurality of words, and the first text information includes a first word among the plurality of words; a UART controller to output the first text information to the WORD table by extracting the first word from output information, and to output an output code based on the output information and the first word code when the first word code is received from the WORD table; and a UART to output debugging information based on the output code.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Embodiments are generally directed to dual role capable connectors for a separable portion of a computing apparatus. An embodiment of an apparatus includes a separable physical connection to a second apparatus; a first electronic connector, the first electronic connector providing data connections for the physical connection; a plurality of additional electronic connectors, the plurality of additional connectors being supported by the first electronic connector; and a control logic to control operation of the plurality of additional electronic connectors, wherein operation of the plurality of additional electronic connectors includes each additional electronic connector being capable to operate in both a host role and a device role for the interconnection of computing systems, wherein the host role and device role may be for a first connector mode or a second connector mode, and an alternative connector mode.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: A storage device for graphic processors and a configuration setting adjusting method are provided. The method includes: obtaining a chassis connection status by a processor according to a first chassis electrically connected to an input/output module; reading a first initial configuration setting in a switching circuit of the first chassis by the processor; obtaining a host connection status by the processor according to at least one first connection interface electrically connected to at least one first host; and determining whether the first initial configuration setting is applicable to the chassis connection status and the host connection status by the processor according to the chassis connection status, the host connection status and a preset rule; if not, adjusting, by the processor, the first initial configuration setting of the first chassis to another configuration setting which is applicable to the chassis connection status and the host connection status.

Abstract: A USB detecting method for use with a controlling and processing unit, a USB input/output port, at least one switch and at least one USB peripheral device is provided. The at least one switch is arranged between the controlling and processing unit and the USB input/output port and/or arranged between the USB input/output port and the at least one USB peripheral device that is electrically connected with the USB input/output port. Firstly, a USB detection signal of the at least one USB peripheral device is provided to the controlling and processing unit. According to a result of receiving the USB detection signal, the controlling and processing unit determines whether the switch is reset. For resetting the at least one switch, the controlling and processing unit simulates the action of plugging and pulling out the USB peripheral device.

Abstract: A USB extension device with dual power supply includes: a first power connection interface of USB Type-C and power transmission specification connected to a first power supply; a second power connection interface connected to a second power supply; a host connection interface of USB Type-C and power transmission specification connected to a host; an external interface connected to an external device; and a power supply management module connected to the first power connection interface, second power connection interface, host connection interface and external interface. When the first and second power connection interfaces are connected to the first and second power supplies respectively, the host supplies power through the host connection interface, and the power supply management module drives the first power supply to supply power to the host, while driving the second power supply to supply power to the power supply management module and to at least one external device.

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Abstract: A Fibre Channel (FC) or FC-over-Ethernet (FCoE) switch has ports to forward Input-Output (IO) requests, and service data transfers, between end devices in a storage area network. The switch receives at a port a time ordered sequence of IO requests for data transfers to be serviced by the port. Each IO request including a data length of the data transfer. The switch detects a microburst on the port for each IO request. To do this, the switch parses the IO request to retrieve the data length, determines a transfer time required to transfer the data length over the port, upon receiving a next IO request, determine whether a time interval between the IO request and the next IO request is less than the transfer time, and if the time interval is less than the transfer time, declaring a microburst on the port, otherwise not declaring a microburst.

Abstract: Moving from a back-to-back topology to a switched topology in an InfiniBand network includes, prior to connecting a switch for a first storage controller in the network and during reboot of the first storage controller, waiting for a second storage controller in the network to become master, and upon the second storage controller becoming master, changing cache files for local ports on the first storage controller regarding adjacent ports' LID assignments. An aspect further includes restarting a system manager for the first storage controller, connecting the first storage controller to the system with new LID assignments provided by changed files on first storage controller, and upon the first storage controller becoming active, rebooting the second storage controller, changing the LID assignments in the active storage controller, and adding new switches to the system.

Abstract: In one embodiment, a networked system includes network interface ports to couple to a computer data network, PCIe devices, bridge devices coupled to network interface ports, a PCIe network switch coupled between bridge devices and PCIe devices, and a configuration device communicatively coupled to bridge devices and PCIe devices. Ports transmit outgoing and receive incoming network traffic. PCIe devices support a function of the computer data network. Each bridge device receives incoming network traffic portions and transmits outgoing network traffic portions through a respective network interface port. PCIe network switch routes PCIe packets between the plurality of bridge devices and the plurality of PCIe devices. Configuration device configures and initializes the PCIe devices for commands and operations that originate from the bridge devices.

Abstract: A power distribution unit (PDU) interface system is disclosed. The PDU interface system receives, from an initiator, an input request associated with a PDU that includes a plurality of ports. The PDU is a first PDU type of a plurality of PDU types. The input request has a same syntax for each of the PDU types. It is determined that the PDU is the first PDU type of the plurality of PDU types. Based on the first PDU type, a first PDU-type input command is initiated to the PDU. The first PDU-type input command implements the input request on the PDU and has a different syntax than the input request.

Abstract: A data communication system is provided. The data communication system includes a data bus, and a line replacement unit including a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus.

Abstract: An extension of the existing CAN FD data transmission protocol. The extension enables the use of the IPv6 protocol for the CAN bus. The CAN FD protocol is further developed in an incompatible way. One modification measure relates to the lengthening of the Data Field, which is positioned in the transmission frame after an Arbitration Field. An arbitrary number of bytes can be entered in the extended Data Field within a specified upper limit. Since the Data Field is transmitted at a higher bit rate field than the Arbitration Field, the data throughput is increased dramatically.

Abstract: An apparatus can include a processor; a controller; a data bus connector; a multiplexer operatively coupled to the data bus connector where the multiplexer includes a controller coupled state operatively coupled to the controller and a processor coupled state operatively coupled to the processor; and circuitry that responds to a signal received via the data bus connector to determine the coupled state of the multiplexer as being one of the controller coupled state and the processor coupled state. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A device includes a first input/output (I/O) port for communication with an external processor, a second I/O port for communication with a second device, and an interface adaptor supporting communication through the first and second I/O ports via a protocol having a plurality of layers, including an application layer, a physical layer, and a physical adaptor layer. The application layer processes information according to an application layer format and the physical adaptor layer processes information according to a physical adaptor layer format. The device receives from the external processor through the first I/O port a request in the application layer format that one or more communication conditions be set for a physical layer of the second device, converts the request from the application layer format to the physical adaptor layer format, and sends the converted request in the physical adaptor layer format to the second device through the second I/O port.

Abstract: In some implementations, a display controller controlling a video input of a display device may select a first set of parameter values from multiple sets of parameter values to configure the video input. After receiving a request from a video source, the display controller may initiate link training. After the link training is completed, the display controller may generate a current link score, determine that the current link score is greater than a stored link score, set a value of the stored link score to be the current link score, and store the first set of parameter values. After selecting each set of parameter values from the multiple sets of parameter values, the display controller may configure the video input of the display device based on the set of parameter values from the multiple sets of parameter values that generated the stored (highest) score.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.