Abstract: A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

Abstract: A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.

Abstract: A compliant support for a display device is described. In one or more implementations, an apparatus includes an external enclosure configured to assume a mobile computing device configuration and one or more computing components secured by and disposed within the external enclosure. The one or more computing components are configured to perform one or more operations that are specified by software. A display device is secured to the external enclosure such that the display device is viewable by a user, the display device supporting touchscreen functionality. A compliant support is disposed between the one or more computing components and the display device, the compliant support configured to reduce deflection of the display device by compression of the compliant support, the deflection caused in response to contact against a surface of the display device.

Abstract: A system and method of operation of a device programming system includes: a socket adapter having a source socket and a destination socket for reading a configuration information from a master device; a partition table calculated from the master device; and a master data file formed from the partition table and the configuration information, the master data file for configuring a programmable device.

Abstract: A method for accessing data stored in a target of a data storage system includes: running a plurality of transport threads on a first group of CPUs, wherein each of the plurality of transport threads comprises a command receiver path and a command transmitter path; running a plurality of data path threads on a second group of CPUs, wherein each of the plurality of data path threads comprises a command issue path and a command completion path; posting an I/O command to an I/O command issue queue using the command receive path of a transport thread, and processing the I/O command using the command issue path of a data path thread; and posting an I/O completion notification to an I/O completion queue using the command completion path of the data path thread, and processing the I/O completion notification using the command transmitter path of the transport thread.

Abstract: An information handling system allocates power for internal use and to support peripheral device operations by managing bi-directional power transfer at plural cable ports. A motion detector disposed in a port detects motion of a cable disconnecting from the port and communicates the motion to a power controller that coordinates termination of power draw from the cable before the power connection between the cable and port is lost.

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

Abstract: In a device and a method for the automated detection of an interface between a position-measuring device and sequential electronics that are interconnected via a data-transmission channel, the position-measuring device includes an interface unit and a position-measuring unit. The interface unit is connected first of all to the data-transmission channel, and secondly to the position-measuring unit for the purpose of an internal data exchange. The interface to the sequential electronics is selectable in the interface unit from at least two interfaces.

Abstract: Systems and methods provide zone management for devices in a Serial Attached Small Computer System Interface (SAS) topology. In one embodiment, a zone management device stores a zone map that identifies an initial zone of a device in the topology. The management device detects changes in the topology, and identifies a current zone of the device subsequent to the change in the topology. The management device compares the zone map for the device to the current zone to identify a change in the zone of the device, and generates a message for an expander in the topology based on the change in the zone. The management device then transmits the message to the expander to restore the zone of the device to the initial zone.

Abstract: A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.

Abstract: Embodiments of the present invention provide a method for accessing an endpoint device in a computer system and a computer system. According to the present invention, an endpoint proxy device establishes a correspondence between a first address, of an endpoint device, in the computing subsystem and a second address, of the endpoint device, in the management subsystem, and when receiving a first access request sent by a management controller to the endpoint device, generates, according to the correspondence, a second access request that carries the first address, of the endpoint device, in the computing subsystem, and sends the second access request to the endpoint device. Therefore, an endpoint device access request of the management controller is sent to the endpoint device, an operation does not need to depend on an operating system, and maintainability in managing the endpoint device is improved.

Abstract: A method and system for managing message-signaled interrupt-based events sent from an event source to a host or a guest is disclosed. A central processing unit instructs an event source to write a message-signaled interrupt to a designated address of a random access memory of the host. The host or a guest of the central processing unit executes a memory monitoring instruction to the designated address. The host or the guest enters a wait state. The host or the guest detects a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. The host or the guest exits from the wait state. The host or the guest performs an atomic operation with respect to the event based on the data items in the message-signaled interrupt.

Abstract: A reproduction device includes a reproduction unit, communication paths, and a communication-path control unit. The reproduction unit is configured to be able to alternatively reproduce content items supplied from sources. The communication paths respectively correspond to the sources. The reproduction unit is connected to the sources via the respective communication paths. The communication-path control unit invalidates, when receiving an instruction to switch to the source having content to be reproduced by the reproduction unit, communication via the communication path corresponding to the source before the switching among the communication paths.

Abstract: A controller includes a descriptor identifier (ID) management block suitable for allocating or deallocating a descriptor ID; a control unit suitable for generating a descriptor corresponding to the descriptor ID, which is allocated by the descriptor ID management block; and an input/output unit suitable for processing a work based on the descriptor, wherein the input/output unit transfers a request for deallocating the descriptor ID to the descriptor ID management block when the work is normally processed.

Abstract: There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.

Abstract: Systems and methods are disclosed, including a USB interface detector, a detection method, a USB connector, and an electronic device. The detection method may be applicable to the USB connector mounted in the electronic device. According to an operation mode of the electronic device, a first pin and a second pin in the USB interface can be pulled up or pulled down. After the pull up or the pull down, a voltage change at the first and second pins are detected. If the voltage changes cross a reference voltage, an instruction related to attachment or detachment with a second device can be provided.

Abstract: A storage system includes an expander sequence including a plurality of expanders coupled in series, a plurality of storage devices coupled to the expander sequence, first and second initiator devices coupled to the expander sequence, and a processor. The processor selects an optimal path, with respect to a transmission destination device of a command among the plurality of storage devices and the plurality of expanders, between the optimal path which is an initiator device with fewer expanders in a distance to the transmission destination device and a roundabout path which is an initiator device with more expanders in a distance to the transmission destination device, and transmits the command to the transmission destination device through the selected optimal path.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. The controller controls the operation of the nonvolatile memory. The interface includes first and second input/output units that transmit and receive a signal with respect to a host device. The first and second input/output units are set on the first hierarchy having the same communication function. The interface issues a connection request to the first input/output unit and when the connection request to the first input/output unit is rejected, the interface issues the connection request to the second input/output unit.

Abstract: In one embodiment, a method of implementing interrupt prioritization and preemption in a modeling environment is provided. The method may include obtaining a model including interrupt-generating components in the modeling environment, obtaining information describing interrupts in the model, and using the information describing the interrupts in the model to automatically generate code for prioritizing the interrupts in the modeling environment.