Patents Examined by Pierre Bataille
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Patent number: 7117203Abstract: Content addressable data storage and compression for semi-persistent computer memory for a database management system including providing a data structure that associates data identifiers and retrieval keys for memory blocks for storing in semi-persistent memory data from the database management system; searching for a segment of a chunk of data from the database management system that matches a memory block from semi-persistent memory; and if a matching segment is found: discarding the matching segment; storing in the data structure in the database management system a retrieval key for the matching segment in association with a data identifier; identifying an unmatched portion of the chunk that does not match the memory block; storing the unmatched portion semi-persistently in a free memory block from a file system; and storing in the data structure in the database management system a retrieval key for the unmatched portion in association with the data identifier.Type: GrantFiled: December 3, 2003Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Michael Gilfix, Anthony N. Liguori
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Patent number: 7117204Abstract: Transparent content addressable data storage and compression for a file system including providing a data structure that associates file identifiers and retrieval keys for memory blocks for storing file contents; storing in the data structure one or more file identifiers; providing a chunk of data comprising a quantity of input data of a file; retrieving a memory block from computer memory; searching for a segment of the chunk that matches the memory block; and if a matching segment is found: discarding the matching segment; providing a retrieval key for the memory block as a retrieval key for the matching segment; identifying an unmatched portion of the chunk that does not match the memory block; storing the unmatched portion; and providing a retrieval key for the unmatched portion.Type: GrantFiled: December 3, 2003Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Michael Gilfix, Anthony N. Liguori
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Patent number: 7114045Abstract: A system and method for intelligent generational garbage collection using a dynamic window. During normal memory allocation, a sliding window defines a young generation within an older generation or other area of memory. When data are stored that will become garbage within a finite period of time, a temporary phase of operation is initiated. In the temporary allocation phase, the lower bound of the window is fixed, while the upper bound is allowed to expand to accommodate new objects. When the data become garbage, the window is garbage collected and compacted, and normal memory allocation and garbage collection operations resume. Thus, the window is dynamic in both movement and size. When the temporary allocation phase is initiated, the young generation may be garbage collected and compacted, and the lower window bound may be fixed at the location (e.g., address) where the allocation point was when the target data were stored.Type: GrantFiled: February 12, 2004Date of Patent: September 26, 2006Assignee: Sun Microsystems, Inc.Inventors: Oleg Pliss, Bernd J. Mathiske
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Patent number: 7114027Abstract: Methods, systems, and products of content addressable data storage and compression for computer memory are disclosed as providing a chunk of data comprising a quantity of input data; retrieving a memory block from computer memory; searching for a segment of the chunk that matches the memory block; and if a matching segment is found: discarding the matching segment and providing a retrieval key for the memory block as a retrieval key for the matching segment; identifying an unmatched portion of the chunk that does not match the memory block; and storing the unmatched portion and providing a retrieval key for the unmatched portion.Type: GrantFiled: December 3, 2003Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Michael Gilfix, Anthony N. Liguori
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Patent number: 7114026Abstract: A content addressable memory (CAM) device having multiple index generators is described. Each of the index generators is coupled to at least one of a plurality CAM blocks. Each of the plurality of CAM blocks includes a CAM block array and a priority encoder. Each of the index generators includes a priority encoder and match enable circuits. Each index generators is configured to receive a block index and a block match flag from a corresponding CAM block and generate a device index corresponding to a highest priority matching entry in a respective CAM block or a group of associated CAM blocks participating in a compare operation.Type: GrantFiled: June 17, 2002Date of Patent: September 26, 2006Inventor: Sandeep Khanna
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Patent number: 7111117Abstract: A method to expand a RAID subsystem from a first array of disk drives to a second array of disk drives. The first array includes a set of data disk drives storing old data and spare space, and the second array includes the first array and at least one new disk drive. First, the old data are distributed among the set of data disk drives and at least one new disk drive while, at the same time, new data are mapped to the spare space. Upon completion of the distribution, the new data are copied from the spare space to the set of data disk drives and at least one new disk drive to enable concurrent expansion of the first array while accessing the old and the new data.Type: GrantFiled: December 19, 2001Date of Patent: September 19, 2006Assignee: Broadcom CorporationInventors: Chris R. Franklin, Jeffrey T. Wong
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Patent number: 7111116Abstract: A method and system for reducing micro-controller access time to information stored in the remote memory via the buffer manager in a disk drive control system comprising a micro-controller, a micro-controller cache system having a plurality of line-cache segments grouped into at least one line-cache segment-group, and a buffer manager communicating with the micro-controller cache system and a remote memory. The method and system includes receiving in the micro-controller cache system a current data-request from the micro-controller, providing the current requested data to the micro-controller if the current requested data resides in a first line-cache segment of a first segment-group, and automatically filling a second line-cache segment of the first segment-group with data retrieved from the remote memory wherein the retrieved data is sequential in the remote memory to the provided current requested data.Type: GrantFiled: September 30, 2003Date of Patent: September 19, 2006Assignee: Western Digital Technologies, Inc.Inventors: William B. Boyle, Robert H. Krebs, Jr.
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Patent number: 7111125Abstract: A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines into the first block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first block of cache lines in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second block of cache lines into the first block of cache lines.Type: GrantFiled: April 2, 2003Date of Patent: September 19, 2006Assignee: IP-First, LLCInventor: Rodney Hooker
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Patent number: 7107405Abstract: In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evicted from the cache.Type: GrantFiled: May 30, 2003Date of Patent: September 12, 2006Assignee: Intel CorporationInventor: John V. Lovelace
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Patent number: 7099988Abstract: A method to read (N) sequential files written to an information storage medium, and then skip the next (M) sequential files. The method initially identifies the (M) files to be skipped. After identifying the (M) files to be skipped, the method reads the (N) files.Type: GrantFiled: August 26, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Kirby G. Dahman, Glen A. Jaquette
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Patent number: 7100010Abstract: A tape cassette of this invention is equipped with a memory capable of accommodating management information. Where the tape cassette is used, a MIC mode switch is written to a predetermined area on the magnetic tape held in the cassette. That item of information specifies whether or not the use of the management information held in the memory is mandatory upon write or read operations to or from the magnetic tape. A check is made on the consistency between the MIC mode switch read from the magnetic tape on the one hand and a result of access to the memory on the other hand. If an inconsistency is detected, that is interpreted as something fraudulent having been committed on the tape cassette. In such a case, read and write operations on the illegitimate cassette are restricted. This improves security of a tape drive system running the tape cassette.Type: GrantFiled: December 31, 2003Date of Patent: August 29, 2006Assignee: Sony CorporationInventors: Tatsuya Kato, Masaki Yoshida, Katsumi Ikeda, Yoshihisa Takayama
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Patent number: 7099996Abstract: A disk array system includes storage devices, a storage device control unit, a connection unit being connected with the storage device control unit, channel control units, a shared memory, and a cache memory. Each channel control unit includes a first processor of converting file data, received through a local area network outside of the disk array system to which the channel control units belongs, into block data and requesting storage of the converted data in the plurality of storage devices and a second processor of transferring the block data to the storage devices through the connection unit and the storage device control unit in response to a request given from the first processor and is connected with the connection unit and the local area network.Type: GrantFiled: February 1, 2005Date of Patent: August 29, 2006Assignee: Hitachi, Ltd.Inventors: Hiroshi Ogasawara, Homare Kanie, Nobuyuki Saika, Yutaka Takata, Shinichi Nakayama
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Patent number: 7096318Abstract: A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.Type: GrantFiled: November 21, 2001Date of Patent: August 22, 2006Assignee: Aspex Technology LimitedInventors: Ian Paul Jalowiecki, John Lancaster, Anargyros Krikelis
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Patent number: 7096317Abstract: The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again.Type: GrantFiled: February 2, 2004Date of Patent: August 22, 2006Assignee: Hitachi, Ltd.Inventors: Masao Inoue, Katsuhiro Okumoto, Hisao Honma
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Patent number: 7096312Abstract: The invention provides a data transfer device for multidimensional memory capable of performing an efficient SIMD operation and suitable for transferring data between a multidimensional memory and a one-dimensional memory. A DMAC reads data of a rectangular area in a logical two-dimensional space of a two-dimensional data access memory, and writes the read data on a one-dimensional data access memory. Further, it reads data from the one-dimensional data access memory, and writes the read data on the two-dimensional data access memory, such that the data are arranged in the rectangular area in the logical two-dimensional space of the two-dimensional data access memory.Type: GrantFiled: March 13, 2003Date of Patent: August 22, 2006Assignee: Seiko Epson CorporationInventor: Toshihiro Kubo
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Patent number: 7093088Abstract: A method and apparatus for managing a migration of a data set from at least one first storage location to at least one second storage location, wherein read requests to the data set from at least one application program executing on a computer system initially are serviced from the at least one first storage location. The data set is copied from the at least one first storage location to the at least one second storage location, and then at least one aspect of the computer system is modified so that read requests to the data set are serviced from the at least one second storage location to achieve the migration. In one embodiment, the migration is subsequently undone by modifying the at least one aspect of the computer system so that read requests to the data set are again serviced from the at least one first storage location. In another embodiment, after the migration is performed, a determination is made as to whether to finalize the migration.Type: GrantFiled: April 23, 2003Date of Patent: August 15, 2006Assignee: EMC CorporationInventors: Stephen J. Todd, Conor Fox, Donagh Buckley, John Philip Bell, II
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Patent number: 7093099Abstract: A processor natively executes lookup instructions. The lookup instruction is decoded to determine which general-purpose register (GPR) contains a pointer to a lookup key in a buffer. A variable-length key is read from the buffer and hashed to generate an index into a first-level cache and a hashed tag. An address of a bucket of entries for the index is generated and tags from these entries are read and compared to the hashed tag. When an entry matches the hashed tag, a second-level entry is read. A stored key from the second-level entry is compared to the input key to determine a match. The addresses of the matching second-level and first-level entries are written to GPR's specified by operands decoded from the lookup instruction. When the key or entry data is long, the second-level entry also contains a pointer to a key extension or data extension in a third-level cache.Type: GrantFiled: April 2, 2003Date of Patent: August 15, 2006Assignee: Alacritech, Inc.Inventors: Amod Bodas, Tarun Kumar Tripathy, Mehul Kharidia, Millind Mittal, J. Sukarno Mertoguno
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Patent number: 7089356Abstract: A method is described for parallel processing of sequence operations, in which contention for the sequence operation is reduced among multiple parallel processes. Contention is reduced by caching sequence values locally for each parallel process. Each process accesses the sequence operation, or an instance level cache of sequence values, in a batched manner, thereby returning a block of unique sequence values instead of a single sequence value. The block of sequence values, or at least information that indicates a range of sequence values that define the block, is then cached locally in association with a given process of the multiple processes. Hence, future requests for sequence values from the given process are serviced from the local cache, rather than having to access the sequence operation and risk contention for the operation with other processes.Type: GrantFiled: November 21, 2002Date of Patent: August 8, 2006Assignee: Oracle International CorporationInventors: Rushan Chen, Bhaskar Ghosh
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Patent number: 7085900Abstract: Provided is a backup device, etc., that updates copy data appropriately. A backup device 300, which records as copy data a copy of original data stored in multiple storage devices 110A to 110D, comprises: a write data storage unit 132, for receiving and storing write data to be written to the original data; and an updating unit 134, for using the write data to update the copy data when update permission data, which permit the use of the write data to update the copy data, are externally received.Type: GrantFiled: May 30, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Takeshi Inagaki, Norie Iwasaki
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Patent number: 7076616Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.Type: GrantFiled: March 24, 2003Date of Patent: July 11, 2006Assignees: Sony Corporation, Sony Electronics Inc.Inventors: Phuong Viet Nguyen, Ashish Garg