Abstract: A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (106-0 to 106-5) in a system (100) having multiple branches (112-0 and 112-1). After chip IDs have been assigned to chips of a first branch (112-0) a command processing system (104) may issue an end of branch indication. Chip IDs may then be assigned to chips of a next branch (112-1).

Abstract: The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural areas which store user data, and restricts access to the user data from a host computer and also dynamically changes an area an access to which is to be restricted. Accordingly, the ease of use of the external storage device for the host computer is improved. Specifically, the interior of the flash memory is divided into a normal area not protected by a password or the like and a protected area protected by a password or the like. A microprocessor controls accesses to the normal area and the protected area in accordance with a command from the host computer. In addition, the host computer can access the protected area after passing through authentication using a password. Moreover, the host computer changes information indicative of the location of the protected area, thereby dynamically changing the protection area.

Abstract: A cache controller structure and method are provided for managing cache access for a computer system. The computer system has a processor having a direction flag and configured to run a repetitive string operation, wherein the string operation is configured to sequentially access a targeted memory block for each repetition depending on the state of the direction flag. A cache controller logic is provided to control a cache embedded in the processor while the processor executes string operations. The cache controller is configured to manipulate the cache lines responsive to the direction flag and to a position of a targeted memory block within a cache line. In some embodiments, the controller logic is also configured to manipulate the cache lines responsive to a repetition parameter value within the string operation.

Abstract: The present invention provides an optical disk drive, optical disk recording method, optical disk recording program and a recording medium having the optical disk recording method recorded therein, applicable to a DVD drive, for example, to permit recording of also a file of still pictures other than moving pictures with a sufficient extension of the recording ability of the optical disk. To this end, individual management information can be accessed via guide information for an extended file in consideration and an identification code CAT ID indicative of the type of the extended file and recording format CAT INFO TYPE of the management information are allocated to the extension-file guide information.

Abstract: A disk array system includes storage devices, a storage device control unit, a connection unit being connected with the storage device control unit, channel control units, a shared memory, and a cache memory. Each channel control unit includes a first processor of converting file data, received through a local area network outside of the disk array system to which the channel control units belongs, into block data and requesting storage of the converted data in the plurality of storage devices and a second processor of transferring the block data to the storage devices through the connection unit and the storage device control unit in response to a request given from the first processor and is connected with the connection unit and the local area network.

Abstract: CAM devices that can be cascaded together to form CAM systems of different sizes are disclosed. The system has one or more clusters of M CAM devices, each device including (M?1) disable connections. Disable signals are used to avoid contention so that one CAM device generates the system output on a shared bus. To reduce pin count, the CAM device of priority N within each cluster has (N?1) of its disable connections programmed as inputs for disable-in signals received from higher-priority CAM devices, and its remaining (M?N) disable connections programmed as outputs for disable-out signals provided to lower-priority CAM devices. Some embodiments include two or more clusters of CAM devices and a controller. In some embodiments, the CAM system works as fast as a single CAM device. Some embodiments impose no architectural limits on the number of CAM devices that can be cascaded together.

Abstract: The present invention provides an optical disk drive, optical disk recording method, optical disk recording program and a recording medium having the optical disk recording method recorded therein, applicable to a DVD drive, for example, to permit recording of also a file of still pictures other than moving pictures, thereby enabling more effective use of the information recording area of the optical disk and more quick search for desired data. To this end, the address of management information (DK) is identified with reference to a management table (TV) recorded in a fixed area on the optical disk, and a recording format is selected for the management information (DK) to be recorded in combination with an extension file (EF).

Abstract: A circuit for generating a Yi control signal in a memory device. The circuit comprises a column select signal control block for generating a Yi control signal for a normal operation of a first cycle of a page mode, a latch for setting the Yi control signal from the column select signal control block, a read reset block for resetting the latch, a page read Yi enable block for generating the Yi control signal when a page address is changed in a page read mode and then setting the latch, and a page read reset block for resetting the latch set by the page read Yi enable block.

Abstract: A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T00 to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock, If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.

Abstract: A method and structure for a system for managing logical blocks of storage is disclosed. An out-of-band mapping unit is adapted to process data requests from a host. The mapping unit includes a first table and a second table. An in-band virtualization engine is operatively connected to the out-of-band mapping unit. The first table is adapted to map to locations on a memory device. The second table is adapted to map to the in-band virtualization engine. The in-band virtualization engine is adapted to perform storage management functions and directly map to the locations on the memory device. The out-of-band mapping unit is adapted to be dynamically altered by the in-band virtualization engine to determine which of the first table and the second table is chosen.

Abstract: Disclosed is a method, system, and program for prestaging data into cache from a storage system in preparation for data transfer operations. A first processing unit communicates data transfer operations to a second processing unit that controls access to the storage system. The first processing unit determines addressable locations in the storage system of data to prestage into cache and generates a data structure capable of indicating contiguous and non-contiguous addressable locations addressable locations in the storage system including the data to prestage into the cache. The first processing unit transmits a prestage command to the second processing unit. The prestage command causes the second processing unit to prestage into cache the data at the addressable locations indicated in the data structure. The first processing unit then requests data at the addressable locations indicated in the data structure. In response, the second processing unit returns the requested data from the cache.

Abstract: An apparatus, program product and method utilize a cache payback parameter for selectively and dynamically disabling caching for potentially cacheable operations performed in connection with a memory. The cache payback parameter is tracked concurrently with the performance of a plurality of cacheable operations on a memory, and is used to determine the effectiveness, or potential payback, of caching in a particular implementation or environment. The selective disabling of caching, in turn, is applied at least to future cacheable operations based upon a determination that the cache payback parameter meets a caching disable threshold.

Abstract: A database manager selectively caches journal entries for certain database changes based on dynamic selection criteria. Preferably, a journal disk drive is provided for storing changes to the database. Database change entries are sequentially cached in a main memory journal buffer, awaiting journal write. When a buffer is filled, its buffer contents are written to the journal disk. However, certain change operations will cause the contents of the buffer to be written to the journal disk immediately, before filling the buffer. Certain database change entries selectively cause the buffer to be written, depending on dynamic selection criteria. Preferably, these selection criteria take into account both the estimated time to recover in the event of a system crash and the current level of activity on the system. Generally, the busier the system, the more data will be cached, and vice versa.

Abstract: The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, large silicon chip area for implementation and slow search speed. The prefix entries are divided in several subgroups. A function is described that can be efficiently implemented to determine which of these subgroups the presented word will find a best match in. Thus, it is necessary to search only this small subgroup of prefixes. This saves on power consumption as well as area. An efficient hardware embodiment of this idea which can search at a very high speed is also presented. The applications for this invention could include internet routing, telephone call routing and string matching.

Abstract: In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and/or written by software/hardware such that the read latency is consistent across multiple devices for reproducibility during debug.

Abstract: The microprocessor is provided with a program modification function not attended with unnecessary branch instructions or interrupt processes. The instruction storage unit includes read-only-memory (ROM) for storing instructions composing a program to be processed and a modified instruction storage unit for storing modified instructions for program modification. When the upper bits of an instruction address supplied from the program counter match with the upper bits of the modifying address, the address translation unit translates the upper bits of the instruction address into the upper bits of the substitutive address where the modified instruction is stored in the modified instruction storage unit.

Abstract: Applicants' invention includes a hard disk drive library which includes a plurality of hard disk drive storage slots, a plurality of backplane connectors, wherein a backplane is disposed in or adjacent to each of the hard disk drive storage slots. Applicants' hard disk drive library further includes one or a plurality of hard disk drives removably disposed in the plurality of storage slots, and a controller in communication with each hard disk drive removably disposed within the hard disk drive library. Applicants' invention further includes a data storage and retrieval system which includes Applicants' hard disk drive library in combination with one or more external servers. Applicants' invention further includes a method to insert additional hard disk drives into Applicants' hard disk drive library. Applicants' invention further includes a method to store data in, and to retrieve data from, the hard disk drives removably disposed in Applicants' hard disk drive library.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Abstract: A disk array connected to a storage area network via a fiber channel has one or more ports each controlled by a processor. Even the disk array with one port and one processor executes online processing and backup processing at the same time while considering an online processing load. A port controller not only accepts a request from a host computer but issues a request to other storage controllers to allow online processing and backup processing to be executed at the same time. In addition, the disk array, if provided with a plurality of ports, selects ports or schedules processing depending upon the load to prevent backup processing from affecting online processing performance.

Abstract: The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An earlier indication can be provided that at least two memory accesses may be required to access a data item by performing a prediction based upon one or more operands generated from a memory instruction instead of waiting for a memory access generation stage to generate the memory access. Prediction logic can generate a prediction signal to prevent the memory access generation stage from receiving signals from a preceding pipeline stage while at least two memory accesses are being generated.