Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A method of rewriting a boot program into a memory device including at least first and second memory blocks to which a boot program can be electrically written and from which a boot program can be electrically erased, includes the steps of (a) erasing data stored in the second memory block to which a new boot program is to be written, (b) writing a new boot program into the second memory block, (c) changing an address of the second memory block such that the second memory block can be recognized as the new primary boot block, (d) erasing an existing boot program from the first memory block, and leaving the second memory block as the primary boot block until a further new boot program is written into the memory device.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.

Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. Redundancy information corresponding to each segment also is distributed randomly over the storage units. The redundancy information for a segment may be a copy of the segment, such that each segment is stored on at least two storage units. The redundancy information also may be based on two or more segments. This random distribution of segments of data and corresponding redundancy information improves both scalability and reliability. When a storage unit fails, its load is distributed evenly over to remaining storage units and its lost data may be recovered because of the redundancy information.

Abstract: A rotating media storage device (RMSD) includes a cache memory and a microprocessor for executing a read caching algorithm for storing data in the cache memory. The microprocessor modifies the read caching algorithm when a vibration state is detected to optimize data transfer rates to and from the media in a vibrating operational environment.

Abstract: Virtual tape libraries are accessed by computer elements such as host computers. A canonical tape module services each tape drive. Each computer element is provided access to at least one logical tape module. Each logical tape module is mapped to a canonical tape module in response to a request to access a tape volume. Thus, each computer element has a logical tape drive capable of accessing any volume on any cartridge in any tape library within the storage system.

Abstract: A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enable reduced data access latency. The compressed memory system implements a system and method for controlling the size of the VUC so as to optimize system performance in a manner which permits the avoidance of operating system intervention which is required in certain circumstances for correct system operation. The system solves-these problems by implementing one or more thresholds, which may be set by the operating system, but which, after being sets control the size of the VUC independently of the operating system or other system software.

Abstract: Backup storage is resynchronized to primary storage, ensuring that any new updates received during resynchronization are applied in the proper order relative to resynchronization data. Under normal operations, a data mover mirrors data stored in primary storage to backup storage. If an error condition arises, preventing mirroring, the data mover stores newly received data in primary storage without mirroring the data to backup storage. The data mover also identifies this data in an update map. When the error condition ends, the data mover performs a static resynchronization process, serving to update the backup storage with the un-mirrored data, identified in the update map. When new data is received during static resynchronization, a dynamic resynchronization process is invoked to accurately process the updates.

Abstract: A semiconductor device comprises an internal circuit and a clock signal switching unit group having M clock signal switching units. m first clock signals and n control signals are input to the clock signal switching unit group (M is not less than m, and M is not less than n). Each of the M clock signal switching units, to which one of the m first clock signals, and an output clock signal from another clock signal switching unit are input, selects one of the m first clock signal and a signal obtained by delaying the output clock signal from another clock signal switching unit, based on the n control signals, and outputs the selected one of the m first clock signal and the signal as an output clock signal. The output clock signal controls the internal circuit.

Abstract: A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.

Abstract: Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache determines that the requesting cache would likely be required to invalidate the cache line soon after receipt, less than the full cache line may be sourced to the requesting cache. The requesting cache will not cache less than a full cache line, but may forward the received data to the processor supported by the requesting cache. Data bus bandwidth utilization may therefore be reduced. Additionally, the need to subsequently invalidate the cache line within the requesting cache is avoided, together with the possibility that the requesting cache will retry an operation requiring invalidation of the cache line.

Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. This random distribution of multiple copies of segments of data improves both scalability and reliability. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all of the storage units.

Abstract: A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner.

Abstract: A victim record table records victim blocks which have been returned from a cache to memory and which are not currently cached in any other caches. If a command affecting a block recorded in the victim record table is received, one or more probes corresponding to the command may be inhibited even if probes would ordinarily be transmitted for the command. System bandwidth which would be consumed by the probes may be conserved. Furthermore, since probes are inhibited, the latency of the command may be reduced since the command may be completed without waiting for any probe responses. Since probes are selectively inhibited if an affected block is recorded in the victim record table, the size of the victim record table may be flexible. If a particular block is not represented in the victim record table, probes are performed when the particular block is accessed (even if the particular block could have been represented in the victim record table but is not because of a limited number of records).

Abstract: Disclosed is a method and an apparatus for enhancing existing caching systems to better support the live broadcast of streaming multimedia over the Internet and other public network systems. The apparatus includes the use of helper servers in the network for supporting high quality live streaming multimedia (SM) broadcasts. The helper servers (HS), also referred to as helpers, are each positioned in the network to be close to some number of clients. Client requests for live SM broadcast objects are re-routed from the content server to the local HS to be serviced therefrom. Servicing requests from the local HS is advantageous in that the requests are not required to be serviced from the content server as separate unicast datastreams thereby reducing network congestion problems. In addition to servicing requests locally, each HS allocates and maintains PH buffers which operate as a form of dynamic cache to further reduce the playback delay at a client.

Abstract: A system, a method, and program products for buffering data from a file in a hierarchical data storage system allocates data buffers and buffer management structures in memory to optimize performance of no recall requests. Buffer management structures, such as buffer headers and hash queue headers, are used to optimize performance of insert, search, and data buffer reuse operations. Buffer headers are managed in a least-recently-used queue in accordance with a relative availability status. Buffer headers are also organized in hash queue structures in accordance with file-based identifiers to facilitate searching for requested data in the buffers. Data buffers can be used to buffer different data blocks within the same file and can be recycled to buffer data from other data blocks and other files from the secondary storage device. Data in a data block may be reread by the requesting process or by other processes as long as the requested data remains valid.

Abstract: This invention involves a method to modify that an operation needs to be done on a file system. This involves the concept of “defragmentation”, which is the process of rewriting parts of a file to contiguous sectors on a hard disk to increase the speed of access and retrieval. The present invention provides a system administrator who sets up a profile of when the file system should have the defragmentation utility run. There would be two fields in the profile; one for the number of times that contiguous allocation failed and the other is the size of the allocation. No application (file system utility) that uses the file system to tell when it is fragmented and that a defragmentation utility needs to be run.

Abstract: Systems and methods are provided to backup, restore and relocate compressed data images, e.g., DASD compressed tracks, associated with virtual storage volumes. A compressed track image of the data is first stored in a storage volume. The data derives from a connected host connected with a control unit that manages the storage volume. When the host data is uncompressed, the control unit compresses the data. In backup, the host reads the compressed data with a read protocol and the control unit assigns metadata to the compressed track. The compressed track is then stored in a backup device, e.g., a tape drive. In restore, the host writes the compressed track to the control unit with a write protocol. If desired, the track is relocated to a different location or to a different storage volume through the associated metadata. In decompression, a seed value is assigned to the data to ensure identification across relocation.

Abstract: A disk drive is disclosed comprising a disk and a semiconductor memory comprising addressable locations for staging and caching data, wherein each addressable location having an allocation status. When a large write command is received from a host to write write-data to the disk, a disk controller dynamically allocates a plurality of the addressable locations relative to the size of the write command and the allocation status of the addressable locations. The write-data received from the host is stored in the dynamically allocated addressable locations while concurrently reading the write-data from the dynamically allocated addressable locations and writing the write-data to the disk. The dynamically allocated addressable locations are re-used for storing write-data received from the host after writing the write-data to the disk.