Abstract: A method for assuring consistency between a primary volume and a remote secondary volume wherein a host CPU manages track-to-track transfers using loosely-coupled, storage control unit mediated, data paths. The method includes initial volume synchronization in which concurrent updates to primary tracks are serialized by the copy progression at the secondary volume according to address. The method further includes volume resynchronization in the event of extrinsic error, fault, or the like in which the status of primary tracks updated during a volume suspension interval utilize bit maps to determine status of tracks unmodified during the suspension interval, and updated tracks and timestamps in addition to addresses. The bit maps and timestamps preserve the most recent version copy order of the tracks on the secondary volume.

Abstract: A method and system for connecting a host to a tape drive for accessing a tape cartridge in a data storage system having a tape library provided with cartridges and tape drives includes the host requesting a desired cartridge to access. In response to the request, a proxy agent queries the library to determine which of the tape drives are available to receive the desired cartridge. The proxy agent then selects a tape drive from the available tape drives to receive the desired cartridge. The desired cartridge is then mounted into the selected tape drive. An access controller then connects a virtual tape drive associated with the host to the selected tape drive to provide the host with access to the desired cartridge. The selected tape drive may be selected as a function of its location with respect to the storage location of the desired cartridge.

Abstract: A method and apparatus for persistent volatile computer memory. In one embodiment, the memory of a computer in partitioned into two regions, one directly accessible to the operating system and one accessible to the operating system only through an intermediary program such as a device driver. In another embodiment, the partitioning of computer memory is achieved through modifications to the computer's BIOS, preventing the operating system from directly addressing a region of volatile computer memory and protecting the contents of the region from modification during a boot cycle.

Abstract: A method, system and apparatus for multicasting or broadcasting a piece of data from one partition of a partitioned computer system to a plurality of partitions of the system are provided. When a partition needs to transfer data to more than one partition of the system, the partition first stores the data into a global memory accessible by all partitions of the system. The memory is then marked “read-only” to ensure that the data is not over-written and the Ids (identifications) of the recipient partitions are passed to a piece of firmware or hardware of the computer system. This firmware or hardware then alerts the recipient partitions that there is a piece of data ready to be read in the memory. Once all the recipient partitions have read the data, the global memory is reverted to a “read” and “write” memory.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A method whereby a computing platform that uses geographic data that are spatially organized into parcels of a given size can specify a parcel block size larger than the given size. Thereafter, during runtime, the geographic data are accessed by the computing platform in groups of one or more parcels not larger than the parcel block size. According to one embodiment, at or after initialization of the computing platform, groupings of parcels corresponding to parcel blocks are determined. Each parcel block has a size larger than the maximum parcel size but not larger than a maximum parcel block size. Data identifying the groupings and the parcels corresponding thereto are stored on the computing platform and the data identifying the groupings and the parcels corresponding thereto are used to access all the parcels corresponding to a parcel block whenever geographic data in any one of the parcels are needed.

Abstract: A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: The present invention provides a generalized method for standard Galois Field operational schemes used in Advanced RAID parity calculations. This method places the standard-field and ring operations in their generalized context of linear operations, which can be described by matrices over the Galois Field with two elements (GF(2)). To ensure recovery of information, certain conditions on these matrices are imposed. A plurality of methods for generating such matrices are provided, thereby increasing the range of computational techniques for parity calculation. Further, the method provides increased flexibility and scope in finding a more efficient computational scheme that is adapted to a particular hardware or software implementation.

Abstract: The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the responses to commands on the system bus. One of the processors generates a snoop response to a command, associated with the same real address as the snooped command, which issued from the processor. In response to a command requesting invalidation of a cache line, a cache within the processor conditionally casts back the cache line to a transition cache in the processor. Based on the system response to the invalidation command, the transition cache either discards the cast back or converts the cast back into a command for writing the cache line in the main memory of the system. The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the system bus.

Abstract: A method and apparatus for quiescing a system storage device wherein cache lines associated with a system storage device to be quiesced are flushed using a stripe lock mechanism to find and flush cache data associated with the given system storage device. Dirty cache lines are associated with a stripe lock, and that stripe lock will be in the active state or the clearing state. The stripe locks are also maintained on a linked list per a system storage device. In the normal life cycle of a stripe lock, if the partner controller requests a lock over part of the extent of an active lock, the active lock will go to the clearing state. Data in the extent of the now clearing lock is flushed. For performing a quiesce, stripe locks for the given system storage device are set to clearing on a plurality of controllers, thus causing the flush. The quiesce mechanism then only needs to wait until stripe locks have been cleared for the system storage device.

Abstract: A system and method for analyzing data accesses to determine data accessing patterns is provided. Data address accesses are traced and transformed into Whole Program Data Accesses (WPDAs). WPDAs may then be used to discover higher-level data abstractions, such as hot data blocks. Hot data blocks provide information related to sequences of data addresses that are repeatedly accessed together. Hot data blocks may then be used to improve program performance.

Abstract: A method and apparatus for loading comparand data into a content addressable memory system. For one embodiment, the CAM system includes a CAM array, a comparand register and select logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments each having a plurality of CAM cells. The comparand register includes a plurality of segments for storing comparand data for comparing with data stored in the CAM array. The select logic selectively enables each segment of the comparand register to store a portion of the comparand data in response to configuration information. The configuration information is indicative of the width and depth of the CAM array. The select logic may also enable each segment of the comparand register to simultaneously load the comparand data.

Abstract: Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.

Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.

Abstract: A CAM system having intra-row configurability. For one embodiment, the CAM system includes a CAM array having a number of rows of CAM cells each segmented into row segments. Each row segment includes a number of CAM cells coupled to a corresponding match line segment. Individual row segments or groups of row segments are uniquely addressable by address logic in response to configuration information that indicates a width and depth configuration of the CAM array. The configuration information may be stored in a configuration register. Data may be communicated with an addressed row segment or group of row segments using data access circuitry. Priority encoding circuitry may be included to generate the address of a row segment or group of row segments that stores data matching comparand data in response to the configuration information.

Abstract: A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in at least one of the row segments in response to first configuration information, and determines when second comparand data matches data stored in at least one group of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

Abstract: A subsystem and a subsystem processing method are disclosed in which a storage control unit 2000 interposed between a plurality of disk units 3000 and a host computer 1000 has a nonvolatile cache 2400 for temporarily holding the read data/write data exchanged between the disk units 3000 and the host computer 1000. The management information for the user data in the cache 2400 is stored in both the in-cache management information area 2420 in the cache 2400 and the in-memory management information area 2221 in a volatile local memory 2210 accessible at high speed. Under normal conditions, the management information in the high speed in-memory management information area 2221 is accessed. At the time of a fault, on the other hand, the management information in the nonvolatile in-cache management information area 2420 is restored in the in-memory management information area 2221, thereby improving the access rate of the cache 2400.

Abstract: A method and apparatus for determining a match address in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information.