Abstract: According to an embodiment, a cache memory control circuit includes: a hit determination section; a refill processing section; a search section configured to determine a refill candidate way by searching for the way candidate for a refill process from a plurality of ways based on an LRU algorithm when the hit determination section detects a cache miss; a binary tree information section configured to store binary tree information for the LRU algorithm; a conflict detection section; and a control section. The control section updates the binary tree information in the binary tree information section by using way information of the way where the refill process is being executed when the conflict detection section determines that the way where the refill process is being executed and the refill candidate way match each other.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: Systems and method are disclosed for processing data storage commands for enclosure services. In one embodiment, a data storage device may include a virtual ATA packet interface (VATAPI). The VATAPI may identify itself as a SCSI enclosure services (SES) device. The VATAPI may allow the data storage device to use SES operations/commands to perform operations/commands for enclosure services.

Abstract: Embodiments disclosed herein provide a high performance content delivery system in which versions of content are cached for servicing web site requests containing the same uniform resource locator (URL). When a page is cached, certain metadata is also stored along with the page. That metadata includes a description of what extra attributes, if any, must be consulted to determine what version of content to serve in response to a request. When a request is fielded, a cache reader consults this metadata at a primary cache address, then extracts the values of attributes, if any are specified, and uses them in conjunction with the URL to search for an appropriate response at a secondary cache address. These attributes may include HTTP request headers, cookies, query string, and session variables. If no entry exists at the secondary address, the request is forwarded to a page generator at the back-end.

Abstract: Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer.

Abstract: One embodiment of the present invention includes a hash selector that facilitates performing effective hashing operations. In operation, the hash selector creates a transformation matrix that reflects specific optimization criteria. For each hash value, the hash selector generates a potential hash value and then computes the rank of a submatrix included in the transformation matrix. Based on this rank in conjunction with the optimization criteria, the hash selector either re-generates the potential hash value or accepts the potential hash value. Advantageously, the optimization criteria may be tailored to create desired correlations between input patterns and the results of performing hashing operations based on the transformation matrix.

Abstract: Embodiments of the present invention provide a method, system and computer program product for dynamic caching module selection for optimized data deduplication. In an embodiment of the invention, a method for dynamic caching module selection for optimized data deduplication is provided. The method includes processing historically relevant byte streams in each of a multiplicity of byte caching modules to populate a table of associations between different classifications of the historically relevant byte streams and correspondingly optimal ones of the multiplicity of the byte caching modules. The method also includes receiving a request to retrieve data from a data source and classifying the request. The method yet further includes consulting the table to identify, from amongst the multiplicity of byte caching modules, a particular byte caching module associated with the classification of the request. Finally, the method includes deduplicating the data in the identified byte caching module.

Abstract: An apparatus, method, and program product for optimizing a multiprocessor computing system by sampling memory reference latencies and adjusting components of the system in response thereto. During execution of processes the computing system, memory reference sampling of memory locations from shared memory of the computing system referenced in the executing processes is performed. Each sampled memory reference collected from sampling is associated with a latency and a physical memory location in the shared memory.

Abstract: A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

Abstract: A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Abstract: A method, according to one embodiment, includes: receiving a recirculation command, performing a coarse page lookup to determine valid ones of logical pages to be recirculated, issuing write commands for the valid logical pages, requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages, receiving verified valid logical pages resulting from the fine page lookup, and sending the write commands corresponding to the verified valid logical pages. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A storage device may include a non-volatile memory; and a controller. The controller may be configured to: operate the data storage device in a standard mode by at least throttling performance, and, responsive to detecting a power loss condition, operate the data storage device in a shutdown mode by at least disabling the throttling.

Abstract: Described embodiments include memory systems that may shadow certain data stored in a first memory device (e.g. NAND flash device) onto a second memory device (e.g. DRAM device). Memory systems may train and/or re-organize stored data to facilitate the selection of data to be shadowed. Initial responses to memory commands may be serviced from the first memory device, which may have a lower latency than the second memory device. The remaining data may be serviced from the second memory device. A controller may begin to access the remaining data while the initial response is being provided from the first memory device, which may reduce the apparent latency associated with the second memory device.

Abstract: A memory module determines that the memory module is connected to a memory module connector. The memory module receives the connector ID from the connector and communicates, to the connector, a memory module ID associated with the memory module. A connector-module ID token is generated using the connector ID and the memory module ID. It is determined that the connector-module ID token was not received from the connector within a predetermined time window. Data on the memory module is erased in response to not receiving the connector-module ID.

Abstract: An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

Abstract: An electronic system, an electronic apparatus, and an access authentication method thereof are provided. The electronic system includes a master apparatus and a slave apparatus. The slave apparatus is coupled to the master apparatus through a serial transmission interface. The slave apparatus includes a data storage unit protected by the slave apparatus with a predetermined key. The master apparatus sends an access request to the data storage unit through the serial transmission interface. The slave apparatus determines whether the master apparatus is allowed to access the data storage unit according to the predetermined key and a key inputted by the master apparatus for authentication.

Abstract: The present invention relates to a storage system of a computer and, more particularly, to a storage system and method having a security storage device including a secured disk area, wherein the existence or absence of the secured disk area cannot be known through the application of an operating system in a deactivated state, and the secured disk area can be activated and used only by a digital key and password when a user's password is input through an application including the digital key.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: Described herein are techniques for arranging a plurality of M.2 solid state drive (SSD) modules and flash storage elements into a compact form factor. On a first side of an SSD sled, a plurality of M.2 SSD modules may be communicatively coupled to a port expander. On a second side of the SSD sled, a plurality of flash storage elements (not packaged into M.2 SSD modules) may be present. A plurality of SSD sleds (with the above-described characteristics) may be sized so as to collectively fit into a single hard disk drive (HDD) compatible compartment of a chassis.