Abstract: A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at least one cache line may be cached in a data processing system and a state of each region, wherein a size of each region corresponds to a plurality of cache lines. The line probe filter directory identifies cache lines cached in the data processing system and a state of each cache line. The controller accesses at least one of the region probe filter directory and the line probe filter directory in response to a memory access request to determine whether to issue the probe, and does not issue any probe in response to a read-only request.

Abstract: A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.

Abstract: In an example, a processing system of a database system may categorize event data taken from logged interactions of users with a multi-tenant information system to provide a metric. Event roll-up aggregate metrics used to provide the metric may be generated in connection with event capture. The processing system of the database system may periodically calculate the metric for a particular one of the tenants, and electronically store the periodically calculated metrics for accessing responsive to a query of the particular tenant.

Abstract: The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data measurement sensors (1, 3, 5), which can operate at various sampling rates. The oldest measurement data sample in the memory (9) is arranged to be read first before the newer measurement data samples. The method comprises: receiving measurement data samples from at least two data measurement sensors (1, 3, 5); and saving the received measurement data samples in the memory (9). Each of the measurement data samples saved in the memory is associated with a tag which is also saved in the memory (9) and which identifies the data measurement sensor (1, 3, 5) which measured the respective measurement data sample.

Abstract: Storage divisions of a non-volatile storage medium may have a writable state and an unwritable state. Storage divisions may be reclaimed by, inter alia, resetting the storage division from an unwritable state to a writable state. Writable storage divisions may be used to service incoming storage requests. If no writable storage divisions are available, requests may stall. One or more storage divisions may be held in a writable state to avoid stall conditions. This, however, may increase the erase dwell time of the storage divisions, which can result in increased wear and reduce the usable life of the storage device. Storage divisions may be prepared for use such that the storage divisions are transitioned to a writable state such that erase dwell time of the storage divisions is reduced, and the storage divisions are available as needed to service incoming requests.

Abstract: A processor including a cache memory, processing logic, access logic, stride mask logic, count logic, arbitration logic, and a prefetcher. The processing logic submits load requests to access cache lines of a memory page. The access logic updates an access vector for the memory page, in which the access logic determines a minimum stride value between successive load requests. The stride mask logic provides a mask vector based on the minimum stride value. The count logic combines the mask vector with the access vector to provide an access count. The arbitration logic triggers a prefetch operation when the access count achieves a predetermined count threshold. The prefetcher performs the prefetch operation using a prefetch address determined by combining the minimum stride value with an address of a last one of the load requests. Direction of the stride may be determined, and a stable mode is described.

Abstract: A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction processing pipeline includes execution logic that executes at least one thread in different protection domains over time, wherein the different protection domains are defined by region descriptors each including first data specifying a memory region of the address space employed by the hierarchical memory system and second data specifying permissions for accessing the associated memory region. The address space can be a virtual address space or a physical address space. The protection domains can be associated with different turfs each representing a collection of region descriptors. A given thread can execute in a particular turf, one turf at a time. The particular turf can be selectively configured to change over time.

Abstract: A method is provided for identifying a lethargic drive. The method includes executing a command directed to at least two drives in a redundant array of independent disks (RAID) configuration. Each of the drives of the at least two drives is associated with a plurality of timing buckets. The method also includes determining a completion time of the command, and, for each of the at least two drives that the command was directed to, counting the completion time of the command in one of the timing buckets associated with the drive.

Abstract: Accessing a circular buffer in memory from a processor may be performed with the aid of precomputed values stored in a pointer descriptor field of a processor storage element, such as a register. The pointer descriptor may store a precomputed value for calculating a memory address in the circular buffer, which may include two values, in which the two values are based, at least in part, on the size of the circular buffer, but neither be the size of the circular buffer. The first value may be used to derive a starting memory location for a circular buffer. The second value may be used in combination with the first value to calculate an end memory location. The start and end locations or addresses, along with the precomputed stored values, are then used to calculate the next address based on the current address of a circular buffer in an efficient manner.

Abstract: A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.

Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.

Abstract: A storage system comprises a storage apparatus and a storage device that is a basis for a storage area provided to the storage apparatus. The storage device determines whether or not a first format that is a format of data stored in the storage device and a second format that is a format of data utilized by the storage apparatus managing the data match with each other, and performs format conversion of either converting data in the first format to data in the second format or converting data in the second format to data in the first format in a case where the first format and the second format do not match with each other.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: Methods and systems for securing sensitive data from security risks associated with direct memory access (“DMA”) by input/output (“I/O”) devices are provided. An enhanced software cryptoprocessor system secures sensitive data using various techniques, including (1) protecting sensitive data by preventing DMA by an I/O device to the portion of the cache that stores the sensitive data, (2) protecting device data by preventing cross-device access to device data using DMA isolation, and (3) protecting the cache by preventing the pessimistic eviction of cache lines on DMA writes to main memory.

Abstract: Provided are computer program product, system, and method for using inactive copy relationships to resynchronize data among n storages referenced as storages 1 through n, wherein n is greater than or equal to three. n?1 active copy relationships are established. Each active copy relationship copies data from one of the storages 1 through n?1 as a source storage to one other of the storages 2 through n as a target storage respectively. At least one inactive copy relationship is established to copy data from one of the storages 1 through n?1 as the source storage to one other of the storages 2 through n as a target storage, such that the source and target storages in the inactive copy relationship are not both also in a same of at least one of the active copy relationships.

Abstract: A nonvolatile memory device includes a memory cell array including a data cell area, and a mode cell area that stores write mode information of the data cell area, a mode information storage block storing previous write mode information read out from the mode cell area in a previous read operation, and a control logic reading out the write mode information from the mode cell area comparing the read-out write mode information and the previous write mode information, and reading the data cell area in a read mode selected based on a comparison result.

Abstract: A computer-implemented method includes receiving a definition of a source guest memory area for utilization by a virtual machine on a source system, wherein the source system includes a source trusted firmware and a source hypervisor. The method restricts write access to the source guest memory area of the virtual machine. The method receives repeatedly a source guest memory page location, content for each of a plurality of source guest memory pages, and an integrity value for each of a plurality of source guest memory page locations. The method receives a global integrity value for integrity values associated with the plurality of source guest memory page locations, wherein a latest integrity values for each of the plurality of source guest memory page locations is utilized. Subsequent to verifying the global integrity value, the method initializes the virtual machine on the source hypervisor.

Abstract: A computer-implemented method includes receiving a definition of a source guest memory area for utilization by a virtual machine on a source system, wherein the source system includes a source trusted firmware and a source hypervisor. The method restricts write access to the source guest memory area of the virtual machine. The method receives repeatedly a source guest memory page location, content for each of a plurality of source guest memory pages, and an integrity value for each of a plurality of source guest memory page locations. The method receives a global integrity value for integrity values associated with the plurality of source guest memory page locations, wherein a latest integrity values for each of the plurality of source guest memory page locations is utilized. Subsequent to verifying the global integrity value, the method initializes the virtual machine on the source hypervisor.

Abstract: A data protecting method for a rewritable non-volatile memory module is provided. The method includes assigning a plurality of physical pages into a plurality of encoding groups to group a first physical page to a first encoding group and group a second physical page to a second encoding group, where each of the physical pages stores user data and a parity code corresponding to the user data, the first physical page is composed of memory cells of a first word line, and the second physical page is composed of memory cells of a second word line adjacent to the first word line. The method also includes respectively encoding the user data in the physical pages of the encoding groups for generating a plurality of group parity codes respectively corresponding to the encoding groups.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.