Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.

Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.

Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

Abstract: A flash translation layer table rebuilding method for a solid state drive is provided. The solid state drive includes a non-volatile memory and a buffering circuit. Firstly, a flash translation layer table is loaded from the non-volatile memory to the buffering circuit. In case that an abnormal shutdown event occurs, plural blocks of the non-volatile memory to be read are determined according to a specified block programming serial number of the flash translation layer table. Then, a read sequence of reading the plural blocks is determined according to a block programming serial number or an auxiliary serial number corresponding to the block. The contents of the blocks are read according to the read sequence. A mapping relationship between plural physical allocation addresses and plural logical block addresses of the flash translation layer table is updated.

Abstract: Organization and management of key-value stores is described. An example method includes providing a stack of tables. Each of the tables includes a set of pages of a pre-determined size for storing a set of key-value entries. The method includes monotonically decreasing a number of pages in the tables according to a position of the table in the stack. The method includes configuring each of the pages in the tables to address a particular range of a key space in such a way that each of the pages in a subsequent table in the stack is configured to address a range addressed by at least two pages in a preceding table in the stack. An action with a key-value entry is carried out by starting with a table in the top of the stack and moving to the next table if the action cannot be carried out.

Abstract: A memory device includes a nonvolatile memory and a memory controller. The memory controller is configured to receive an access command with respect to a cluster of the nonvolatile memory, the access command including a size of the cluster and a logical address corresponding to a part of the cluster, translate the logical address to a physical address in the nonvolatile memory, by referring to a table storing physical addresses corresponding to part of logical addresses of the nonvolatile memory, identify all physical addresses corresponding to the cluster, based on the size of the cluster, the translated physical address, and an algorithm that generates a sequence for accessing the nonvolatile memory, and access the cluster of the nonvolatile memory in accordance with the identified physical addresses.

Abstract: A technique recovers from a low space condition associated with storage space reserved in an extent store to accommodate write requests received from a host and associated metadata managed by a layered file system of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The write requests, including user data, are persistently recorded on non-volatile random access memory (NVRAM) prior to returning an acknowledgement to the host by a persistence layer of the storage I/O stack. Volume metadata managed by a volume layer of the layered file system is embodied as mappings from logical block addresses (LBAs) of a logical unit (LUN) accessible by the host to extent keys maintained by an extent store layer of the layered file system. Extent store metadata managed by the extent store layer is embodied as mappings from the extent keys to the storage locations of the extents on storage devices of storage arrays coupled to the nodes of the cluster.

Abstract: A data deployment determination apparatus includes a correlation information creation processor that creates correlation information in which addresses indicating areas in a first memory are correlated with frequency information on memory accesses for the respective addresses, from trace information on a memory access to the first memory, a time reduction calculation processor that calculates, for each of the addresses, time reduction in memory accesses to data stored in the first memory based on the correlation information when data stored in the first memory is stored in a second memory which is a memory having a larger bandwidth than the first memory, and a data deployment determination processor that determines that first data stored in the address of which the time reduction is larger than the time reduction corresponding to second data stored in the address is to be stored in the second memory in preference to the second data.

Abstract: A method, device, and non-transitory computer readable medium that dynamically allocates cache resources includes monitoring a hit or miss rate of a service level objective for each of a plurality of prior workloads and a performance of each of a plurality of cache storage resources. At least one configuration for the cache storage resources for one or more current workloads is determined based at least on a service level objective for each of the current workloads, the monitored hit or miss rate for each of the plurality of prior workloads and the monitored performance of each of the plurality of cache storage resources. The cache storage resources are dynamically partitioned among each of the current workloads based on the determined configuration.

Abstract: Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block RAM such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address <addr> is provided to the block RAM and the address increment signal is asserted, data may be read from location <addr+N> instead of <addr>, where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.

Abstract: The present invention relates to a method for a page-level address mapping based on flash memory and a system thereof. A method for a page-level address mapping based on a flash memory according to an embodiment of the present invention includes the steps of: receiving a write operation from a file system; generating condensed mapping information using a size of data information of the write operation and a start logical address of sequentially allocated logical addresses of the write operation; and storing the condensed mapping information as a first mapping table in a memory of a flash translation.

Abstract: A storage control device that is any of a plurality of storage control devices configured to control access to a plurality of storages included in a storage system, includes: a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: executing, depending on a first bias for accessing a plurality of storage regions included in the plurality of storages, a first configuration change which corrects the first bias based on configuration information identifying a configuration of the storage system; and executing, depending on a second bias for accessing the plurality of storages, a second configuration change which corrects the second bias based on the configuration information after changing the first configuration, or executing, depending on a third bias for loading the plurality of storage control devices, a third configuration change which corrects the third bias.

Abstract: Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

Abstract: The present application relates to a heap sorting method based on arrangement and apparatus which can improve the heap sorting conducting speed through reducing access (I/O) frequency of the external memory when conducting heap sorting through storing binary data in the basic access unit of the external memory device in reference to the subtree unit.

Abstract: A system, method, and apparatus are provided for performing a transparent hybrid data storage scheme in which data are stored as blocks distributed among one or more flash-based storage devices (e.g., solid state drives) and one or more magnetic storage devices (e.g., magnetic disk drives). Files larger than a given size (e.g., 1 MB) are segmented into blocks of that size and stored on one or more devices; blocks of one file may be stored on devices of different types. Periodically, a utility function calculates utility values for each of some or all stored blocks based on frequency of access to the block, frequency of access of a particular type (e.g., random, sequential), a preference regarding where to store the block or the corresponding file, and/or other factors. Blocks having the highest utility values are subject to migration between devices of different types and/or the same type (e.g., for load-balancing).

Abstract: A storage unit controller and a control method thereof, and a storage device are provided. The storage unit controller includes an address mapping unit, a nonvolatile buffer and an update indicator. The update indicator sets an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit. The address mapping unit checks the indicated flag when power is on. When the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode so as to perform background operations: the first data has not yet been successfully addressed to the storage unit previously, but saved in a simulated address of the nonvolatile buffer to transfer the first data from the simulated address to an actual address of the storage unit.

Abstract: An integrated circuit may have processing and storage circuits that perform read-modify-write operations on a wide data path. A CAD tool may partition the wide data path into data path subsets based on the width of the wide data path, the characteristics of the processing and storage circuits, and various constraints such as resource constraints and timing constraints. The CAD tool may also instantiate corresponding pipelined circuitry. The pipelined circuitry may be arranged in slices with cascaded processing and storage circuits. Each processing and storage circuit in a slice may perform a read-modify-write operation based on the corresponding data path subset and any prior result produced by other processing and storage circuits.

Abstract: A method or system for determining a required certification level of storage area for storing data of a write request based on a characteristic of the data, selecting a target storage area based on a media certification table and the required determined certification level of the media area and storing data at the target storage area.

Abstract: A storage device includes a nonvolatile memory and a memory controller. The nonvolatile memory performs read, write, and erase operations. The memory controller operates in an operating mode where the memory controller exchanges a voltage signal, set to a reference voltage level within an allowable range, with the nonvolatile memory or receives the voltage signal from an external device. When operating in the operating mode, the memory controller optimizes an operating frequency of the nonvolatile memory depending on a voltage level of the voltage signal and a temperature.

Abstract: An information processing apparatus comprises: a programmable circuit unit comprising a partial reconfiguration unit; a storage unit used by each of logic circuits configured in the partial reconfiguration unit; and a control unit that controls a logic circuit that becomes an access destination, in accordance with receiving an access command, wherein the control unit compares an address space indicating the access destination of the access command with the signal that is output from the partial reconfiguration unit due to the partial reconfiguration unit being configured using circuit information included in the configuration data, and controls to set as an access destination the logic circuit configured in the partial reconfiguration unit outputting the signal matching the address space indicating the access destination of the access command.