Abstract: Method, system, and computer program product for dynamic address translation for a virtual machine are disclosed. The method includes obtaining a memory portion from a memory space, in response to a request for building a shadow dynamic address translation table, wherein the memory space is allocated for at least one guest operation system and wherein the shadow dynamic address translation table includes a mapping between at least one guest logic memory address and at least one host physical memory address. The method further includes building the shadow dynamic address translation table and storing the shadow dynamic address translation table in the memory portion.

Abstract: A method is described that includes generating, by a controller of a storage device, operating statistics associated with an operating state of the storage device. The method includes receiving, by the controller and from a host device, a non-interrupt command frame that requests transfer of data blocks between the storage device and the host device. The method further includes, in response to receiving the non-interrupt command frame, generating, by the controller, a response frame associated with the non-interrupt command frame, wherein the response frame includes the operating statistics. The method includes transmitting, by the controller and to the host device, the response frame.

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

Abstract: In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been received, determine one or more second systems that each have subscribed to be notified when the value of the user datum is updated and each have a pre-established relationship with the user associated with the user datum; and push notifications to the second systems indicating that the value of the user datum has been updated without providing the updated value for the user datum to the second systems.

Abstract: Methods, computer media encoding instructions, and systems that receive write requests directed to non-sequential logical block addresses and write the write requests to sequential disk block addresses in a storage system include an overprovision of a storage system to include an increment of additional storage space such that it is more likely a large enough sequential block of storage will be available to accommodate incoming write requests.

Abstract: Systems and procedures are provided to enable fixed block architecture (FBA) device support over fiber connections using transport mode protocol. The FBA devices may have a size greater than 2 terabytes. The system may be used with existing fixed block command sets according to the transport mode protocol. The existing fixed block command sets may be extended to permit addressing of greater than 2 terabytes. The transport mode protocol may be based on a high performance protocol implementation that facilitates processing of I/O requests.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: Provided are a computer program product, system, and method for using inactive copy relationships to resynchronize data between storages. A first and second groups of active copy relationships are established to serially copy data among the storages in the first and second groups, respectively. At least one of the storages in both the first group and the second group comprise overlapping storages that are members of both the first and second groups and at least one of the storages in both the first and second groups comprise non-overlapping storages that are a member of only one of the first and second groups. At least one inactive copy relationship is established having as a source storage one of the non-overlapping storages in the first group and as a target storage one of the non-overlapping storages in the second group.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link. The processor issues a routing command to an optical circuit switch (OCS) through an OCS control line. In response to the routing command, the OCS establishes a routing of an optical memory link from the processor to the BDM. In response to the establishment of the optical memory link from the processor to the BDM, the processor (or a BDM (internal/dedicated) controller) switches from performing the process through the electrical memory link to performing a process through the optical memory link (continuously without an interruption between the successive processes). Corresponding systems are also disclosed herein.

Abstract: A memory system and method for delta writes are provided. In one embodiment, a memory system receives a request to store data in the memory and determines whether the data requested to be stored in the memory is a modified version of data already stored in the memory. If it is, the memory system compares the data requested to be stored in the memory with the data already stored in the memory to identify differences between the data to be stored and the data already stored. The memory system then stores the identified differences in the memory, along with a table that maps the stored identified differences to corresponding locations in the data already stored in the memory. Other embodiments are provided.

Abstract: A system and method for using a Solid State Drive (SSD) (505) are described. Reception circuitry (510) may receive write requests (1610, 1615, 1620, 1625) and invalidate requests (1630, 1635, 1640) from a first stream (305, 320, 335, 350). The write requests (1610, 1615, 1620, 1625) may request that data be written to storage (520) on the SSD (505); invalidate requests (1630, 1635, 1640) may invalidate data written to the storage (520). A statistics calculation logic (1705) may calculate statistics (1410, 1415, 1510) for the stream based on the write requests (1610, 1615, 1620, 1625) and the invalidate requests (1630, 1635, 1640). A performance logic (1710) may use the calculated statistics (1410, 1415, 1510) to improve the performance of the SSD (505).

Abstract: Described are various SoC fabric extensions for configurable memory mapping. A memory request datapath may transmit a memory request. A first circuitry may identify any memory request having an address between a base-address and limit-address. A second circuitry may transmit to a memory interface any memory request that is identified by the first circuitry, and to apply a default memory access protocol to any memory request that is unidentified by the first circuitry. A third circuitry may modify an address of a memory request when both a multiple-memory-interface indicator and an address-flattening indicator are asserted.

Abstract: A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.

Abstract: A data caching method is disclosed. The method comprises changing, according to an instruction, a cache value, corresponding to a key, in a cache on a volatile memory, recording the instruction following a first effective content of a log file in a non-volatile memory to obtain a second effective content, the second effective content including the first effective content and the recorded instruction, and storing the key and the changed cache value corresponding to the key into the non-volatile memory.

Abstract: Disclosed herein are various systems and methods for sharing a storage device with multiple virtual machines are disclosed. One such method involves creating a pseudo-identity for a storage device and assigning a portion of an address space of the storage device to a virtual machine using the pseudo-identity. The storage device is coupled to a computing device and the pseudo-identity is created by a hypervisor associated with the computing device. The pseudo-identity facilitates access to the storage device by the virtual machine associated with the hypervisor and also facilitates presentation of one or more physical characteristics of the storage device to the virtual machine. The method also assigns a portion of an address space of the storage device to the virtual machine using the pseudo-identity.

Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.

Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.

Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.