Abstract: A storage apparatus has a tiered pool including a plurality of storage tiers formed by a plurality of real page groups having different input/output performance and provides a virtual volume to which a storage area is allocated by a real page unit. At a time point before new data to be written to the virtual volume occurs based on a data object, if a real page is allocated to a write destination virtual page which is a write destination of the new data, a host computer transmits a change command to change the real page allocated to the write destination virtual page to a real page in a storage tier having predetermined performance to the storage apparatus. The storage apparatus changes the real page allocated to the write destination virtual page to a real page in the storage tier having the predetermined performance according to the change command.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

Abstract: A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Abstract: Methods, computer media encoding instructions, and systems that receive write requests directed to non-sequential logical block addresses and write the write requests to sequential disk block addresses in a storage system include an overprovision of a storage system to include an increment of additional storage space such that it is more likely a large enough sequential block of storage will be available to accommodate incoming write requests.

Abstract: Mapping an address for memory access in a memory system into a combination address that includes a memory bank identifier and a memory bank internal address. The address is partitioned into a first portion, and a second portion. The memory bank identifier is determined by performing a look-up operation in a look-up matrix, in which a look-up matrix row is determined by the value of the first portion, and a look-up matrix column is determined by the value of a binary number with two or more bits formed by applying a parity function to two or more respective sub-portions of the second portion. The memory bank internal address is derived based on the second portion of the address.

Abstract: Disclosed is a baseboard management controller (BMC) that may include a bootloader, and an interface to a removable storage device having a first firmware file. The bootloader may be configured to load the first firmware file from the removable storage device for the BMC to run a kernel.

Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

Abstract: A data storage device include a storage memory, an information memory suitable for storing disk information and/or file information transmitted from a host device, and a controller suitable for processing a request on the data memory, which is received from the host device, based on the disk information and/or the file information stored in the information memory.

Abstract: Disclosed is a baseboard management controller (BMC) that may include a bootloader, and an interface to a removable storage device having a first firmware file. The bootloader may be configured to load the first firmware file from the removable storage device for the BMC to run a kernel.

Abstract: Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.

Abstract: A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

Abstract: A system and method of improved communication in a storage network includes a storage node. The storage node includes a control unit and a plurality of local ports coupled to the control unit and configured to couple the storage node to a storage network. The control unit is configured to discover port addresses of other storage nodes in the storage network, select a first port pair including a first source port selected from the local ports and a first destination port selected from remote ports associated with the port addresses of a first one of the other storage nodes, open a first connection between the first source port and the first destination port, determine whether a less desirable notice associated with the first port pair is received, and when the less desirable notice is received, record the first port pair as being less desirable.

Abstract: An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region. Two NVMMCS (non-volatile memory management controllers) are respectively coupled to the two regions. A programming command-and-address decoder is coupled to the NVMMCS. The programming command-and-address decoder instructs the first NVMMC to erase data from the first region when receiving a command to erase the first region via a programming interface, and instructs the second NVMMC to erase data from the second region when receiving a command to erase the second region via the programming interface.

Abstract: A packet processing apparatus includes a processor configured to execute a process. The process includes: determining a memory from which packets are read, out of a first memory that stores the packets and a second memory that stores the packets, in accordance with number of pointers indicative of storage locations of the packets in the first memory; and reading the packets stored at the storage locations indicated by the pointers, from the memory determined at the determining.

Abstract: A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.

Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.

Abstract: Provided are a computer program product, system, and method for modeling workload information for a primary storage and a secondary storage. A determination is made of: a first type and second type of Input/Output (I/O) operations with respect to extents configured in the primary storage; a cumulative I/O workload for the primary storage based on a first type and a second type of I/O operations at different cumulative storage amounts of the primary storage indicating a concentration of the I/O workload on the primary storage; and cumulative I/O workload for the secondary storage based on the first type and the second type of I/O operations at different storage amounts indicating a concentration of the I/O workload of the first type of I/O operations on the secondary storage. A performance gap is determined based on the cumulative I/O workloads for the primary and secondary storages at one of the storage amounts.

Abstract: A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.