Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Abstract: A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

Abstract: Garbage collection is performed for a virtualized storage system whose virtual address space is addressed in extents. Valid data in source extents is copied via a cache into destination extents. Once all valid data in a source extent is copied into one or more destination extents, the source extent may be reused. A source extent is released for reuse only after the one or more destination extents that received the valid data copied from the source extent are determined to be full, and the valid data copied from the source extent to the destination extent via the cache is flushed out of the cache.

Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.

Abstract: Replicas of content can be managed in storage systems. In one example, a storage system can determine an amount of load on the storage system based on values for performance metrics indicating a performance of the storage system. Next, the storage system can determine that the storage system is to have a target number of replicas of content based on the amount of load on the storage system. The storage system can then adjust itself to have the target number of replicas of the content.

Abstract: Systems and methods for dynamically placing data in a hybrid memory structure are provided. A machine learning (ML)-based, adaptive tiered memory system can actively monitor application memory to dynamically place the right data in the right memory tier at the right time. The memory system can use reinforcement learning to perform dynamic tier placement of memory pages.

Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.

Abstract: A storage device includes a nonvolatile memory including a main meta data area and a journal area, and a controller. The controller updates an address mapping table including a plurality of page mapping entries divided into a plurality of segments by executing a flash translation layer (FTL) stored in a working memory, stores updated page mapping entries of the plurality of page mapping entries in the journal area as journal data, and stores the plurality of segments, each having a size smaller than a physical page of the nonvolatile memory, in the main meta data area.

Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

Abstract: An apparatus and method are disclosed for managing cache coherency. The apparatus has a plurality of agents with cache storage for caching data, and coherency control circuitry for acting as a point of coherency for the data by implementing a cache coherency protocol. In accordance with the cache coherency protocol the coherency control circuitry responds to certain coherency events by issuing coherency messages to one or more of the agents. A given agent is arranged, prior to entering a given state in which its cache storage is unused, to perform a flush operation in respect of its cache storage that may cause one or more evict messages to be issued to the coherency control circuitry. Further, once all evict messages resulting from performance of the flush operation has been issued, the given agent issues an evict barrier message to the coherency control circuitry.

Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided. The method includes: selecting at least one first physical unit and at least one second physical unit from the physical units; reading first mapping information from the rewritable non-volatile memory module, and the first mapping information includes mapping information of the first physical unit and mapping information of the second physical unit; copying valid data collected from the first physical unit and valid data collected from the second physical unit to at least one third physical unit of the physical units according to the first mapping information; and when a data volume of valid data copied from the second physical unit to the third physical unit reaches a data volume threshold, stopping collecting valid data from the second physical unit, and continuing collecting valid data from the first physical unit.

Abstract: A data storage device includes a memory array including a plurality of memory cells; and a controller in communication with the memory array and configured to: store, in a map update buffer, one or more map segments including one or more logical address to be unmapped; determine, among logical address to physical address (L2P) entries of the one or more map segments stored in the map update buffer, L2P entries having the same memory block number; and selectively perform a first unmap operation or a second unmap operation according to whether all the L2P entries stored in the map update buffer have the same memory block number.

Abstract: Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.

Abstract: A data storage apparatus includes a volatile memory, the volatile memory including a region in which a zone mapping table and system information are stored and a random access zone capable of random write. The data storage apparatus further includes a non-volatile memory including a backup zone and a plurality of sequential zones capable of sequential write, and a controller configured to identify whether a logical address belongs to the random access zone or the sequential zone when the logical address and a data size are received along with a write command or read command from a host apparatus and to control an operation corresponding to the write command or read command.

Abstract: A remote agent for providing data protection services includes persistent storage and a backup orchestrator. The persistent storage stores lifecycle policies. The backup orchestrator instantiates a backup agent in a client in response to a backup generation for the client, the backup generation is specified by the lifecycle policies; using the backup agent: generating a backup including backup data for the client and backup metadata that associates portions of the backup data with respective persons; and storing the backup in backup storage based on the lifecycle policies.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.

Abstract: Described herein is a system, and related techniques, for predicting I/O requests that are not necessarily directed to sequential sectors of a physical storage device. In some embodiments, I/O patterns that do not involve sequential-sector access, and that may be relatively long-term patterns, may be recognized. To recognize such patterns, deep machine-learning techniques may be used, for example, using neural networks. Such neural networks may be a recurrent neural network such as, for example, an LSTM-RNN. I/O streams for a workstream may be sampled for specific I/O features to produce a time series of I/O feature values of a workstream, and this time series of data may be fed to a prediction engine, e.g., an LSTM-RNN to predict one or more future I/O features values, and I/O actions may be taken based on these predicted feature values.

Abstract: A technique for managing write requests in a data storage system checks whether newly-arriving data match previously-stored data that have been recorded in a deduplication database. If a match is found, the technique compares mapping metadata for the newly-arriving data with mapping metadata for the matching data. If both sets of metadata point to the same storage location, then the newly-arriving data is a same-data write and a new write to disk is avoided.

Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.

Abstract: A data storage system performs updating of a set of global counters stored in persistent storage accessible to a plurality of processing nodes of a data storage system, the global counters storing respective global count values describing associated units of data storage shared by the processing nodes for performing data storage operations. The updating includes, by each processing node, using a respective set of in-memory delta counters storing respective delta count values to track changes to respective global count values due to data storage operations performed by the processing node with respect to the units of data storage. A summarization process is regularly executed to merge the delta count values of the delta counters of all processing nodes into the respective global counters.