Patents Examined by Prasith Thammavong
  • Patent number: 11144210
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11144476
    Abstract: An apparatus includes a cache controller circuit and a multi-ported cache memory including a plurality of cache ways. The cache controller circuit is configured to maintain rank values and a threshold value usable to classify the rank values. A given rank value corresponds to a least recently used one of the plurality of cache ways. The cache controller circuit is further configured to receive, in a common access cycle, first and second memory access requests for the cache memory, and, in response to a determination that the first and second memory access requests correspond to respective first and a second cache ways, compare the corresponding rank values for the first and second cache ways to the threshold value. The cache controller circuit is further configured to, based on the comparison, modify the rank value of a selected one of the first and second cache ways.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Apple Inc.
    Inventors: Chance C. Coats, Haldun Umur Darbaz
  • Patent number: 11144449
    Abstract: An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11144478
    Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11132291
    Abstract: One embodiment facilitates data storage. During operation, the system receives data to be stored in a non-volatile memory of a storage device. The system determines, by a flash translation layer module of a control unit which is distinct from the storage device, a physical page address at which the data is to be stored in the non-volatile memory, wherein the flash translation layer module of the control unit determines physical page addresses for data to be stored in a plurality of storage devices. The system stores, by the flash translation layer module of the control unit, a mapping between a logical page address for the data and the physical page address. The system writes the data to the non-volatile memory at the physical page address.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 28, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Patent number: 11126358
    Abstract: An apparatus in one embodiment comprises a host device configured to communicate with a storage system. Responsive to an instruction to migrate data from a source volume to a destination volume, the host device replaces an input-output entry function of a source pathing device associated with the source volume with a migration input-output entry function that is configured, in response to receiving an input-output operation, to call an input-output entry function of a destination pathing device associated with the destination volume and to call the input-output entry function of the source pathing device. Responsive to an indication that a migration of data has completed, the host device replaces the migration input-output entry function with a post-migration input-output entry function. The post-migration input-output function is configured to call the input-output entry function of the destination pathing device in response to receiving an input-output operation.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: September 21, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kundan Kumar, Kurumurthy Gokam, Shubham Sharma
  • Patent number: 11119864
    Abstract: A method, system and computer program product for achieving activity centric computing. An activity (e.g., opening an application, opening an electronic communication, initiating a printing action, initiating a browsing session) performed by a user on a computing device is detected. In response to detecting the activity, the runtime environment is captured and the session workflow associated with the detected activity is recorded. The session workflow refers to the events performed by the user on the computing device in connection with performing an activity (e.g., application usage, web browsing) on the computing device. The captured runtime environment and the recorded session workflow associated with the detected activity are stored in a portable container. After receiving an indication to share the activity, an image of the container is created and stored in a repository to be shared among users to replay the session workflow associated with the activity.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nitin S. Jadhav, Shailendra Moyal, Akash U. Dhoot
  • Patent number: 11112990
    Abstract: Managing storage device evacuation that includes a plurality of storage devices, including: detecting, by the storage system, an occurrence of a storage device evacuation event associated with a source storage device within a write group, wherein the write group is a subset of storage devices storing a data set; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage system, a target storage device for receiving data stored on the source storage device; and migrating, by the storage system, the data stored on the source storage device to the target storage device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 7, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, John Colgrove, Taher Vohra, Andrew Kleinerman, Xiaohui Wang, Benjamin Scholbrock
  • Patent number: 11106545
    Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 31, 2021
    Assignee: Rubrik, Inc.
    Inventors: Benjamin Travis Meadowcroft, Li Ding, Shaomin Chen, Hardik Vohra, Arijit Banerjee, Abhay Mitra, Kushaagra Goyal, Arnav Gautum Mishra, Samir Rishi Chaudhry, Suman Swaroop, Kunal Sean Munshani, Mudit Malpani
  • Patent number: 11093159
    Abstract: An apparatus is configured to identify a storage volume to be added to a consistency group for replication from a source storage system (“source”) to a target storage system (“target”), to generate a snapshot of the storage volume, to create a dummy volume on the target, to copy the snapshot to the dummy volume, and to add the storage volume to the consistency group. In conjunction with replication of the consistency group from the source to the target, a determination is made for each of a plurality of data pages of the storage volume whether or not the data page already exists in the target as part of the dummy volume. For at least one data page that already exists in the target as part of the dummy volume, a reference count is incremented in the target for that data page instead of copying that data page from the source.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Xiangping Chen
  • Patent number: 11086529
    Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 10, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Tao, Niang-Chu Chen
  • Patent number: 11086518
    Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at least one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventor: Beom Ju Shin
  • Patent number: 11079954
    Abstract: A deduplication memory system includes a virtual memory space, a physical memory space and a memory manager. The memory manager generates a user data entry that is stored in the physical memory space. The user data entry represents a unique user data of a predetermined granularity appearing in the virtual memory space, and includes first and second portions. The first portion includes information relating to a number of duplication times the unique user data corresponding to the user data entry is duplicated in the virtual memory space, and the second portion includes a selected part of the unique user data from which the unique user data may be reconstructed. The first portion may include an index to an extended reference counter table or a special data pattern table if the number of duplication times of the unique user data is greater than or equal to a predetermined number.
    Type: Grant
    Filed: November 4, 2018
    Date of Patent: August 3, 2021
    Inventors: Dongyan Jiang, Qiang Peng, Andrew Chang, Hongzhong Zheng
  • Patent number: 11074003
    Abstract: A storage controller configures a plurality of logical volumes, a CDP meta volume that manages history information related to writing from a server system for the logical volumes, and a CDP data volume that stores data of the plurality of logical volumes. The storage controller searches for, if a restoration request including a restoration time is received, the restoration request having one of the plurality of volumes as a restoration target volume, history information of the restoration target volume from the CDP meta volume, copies, in a case in which an evacuation time of old data included in the searched history information of the restoration target volume is newer than the restoration time, an SEQ number of the searched history information as first restoration control information, and acquires old history information on the basis of a previous SEQ number of the restoration target volume from the CDP meta volume.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: July 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ryosuke Kodaira, Naoyuki Masuda
  • Patent number: 11055023
    Abstract: An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: July 6, 2021
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Shih-Fu Huang, Yi-Lin Hsieh, Cheng-Yu Chen
  • Patent number: 11048413
    Abstract: A decompression system includes a first memory including a first write port configured to receive decompressed data from a decompressor, and a first read port configured to receive a back-reference read request, the first memory being configured to output the decompressed data to the decompressor in response to receiving the back-reference read request at the first read port, and a second memory including a second write port electrically coupled to the first write port and configured to receive the decompressed data, the second memory being configured to buffer the decompressed data for retrieval by a receiver.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 29, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Huzaifa S. Ginwalla, Ramdas P. Kachare
  • Patent number: 11030135
    Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 8, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Greg Sadowski
  • Patent number: 11029881
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Patent number: 11030088
    Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Jongmin Gim, Hongzhong Zheng
  • Patent number: 11030093
    Abstract: A high efficiency garbage collection method, an associated data storage device and a controller thereof are provided. The high efficiency garbage collection method includes: starting and executing a garbage collection procedure; determining whether a Trim command from a host device is received; in response to the Trim command being received, determining whether target data of the Trim command is stored in a source block of the garbage collection procedure; in response to the target data being stored in the source block, determining whether the target data stored in the source block has been copied to a destination block of the garbage collection procedure; and in response to the target data stored in the source block having been copied to the destination block, changing at least one physical address of the target data of the Trim command to a Trim tag in a logical-to-physical address mapping table.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Ting-Heng Chou, Jian-Wei Sun