Patents Examined by Quovaunda V Jefferson
  • Patent number: 10439156
    Abstract: Provided is a light-emitting element which has an anode, a light-emitting layer over the anode, an electron-transport layer over and in contact with the light-emitting layer, an electron-injection layer over and in contact with the electron-transport layer, and a cathode over and in contact with the electron-injection layer. The light-emitting layer has an electron-transport property, and the electron-transport layer includes an anthracene derivative. The light-emitting layer further includes a phosphorescent substance. This device structure allows the formation of a highly efficient blue-emissive light-emitting element even though the phosphorescent substance has higher triplet energy than the anthracene derivative which directly contacts with the light-emitting layer.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Takahiro Ishisone, Satoshi Seo, Takeyoshi Watabe
  • Patent number: 10410975
    Abstract: A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 10, 2019
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Bruce Scatchard, Peter Onufryk, Chunfang Xie
  • Patent number: 10367126
    Abstract: A light-emitting device includes a base having an insulating part and a metal block; a light-emitting diode (LED) chip over the base; a water soluble paste between the LED chip and the base metal block for chip fixing and heat conduction; packaging glue covering the LED chip; and the LED chip bottom, water soluble paste and the base metal block form an all-metal thermal conducting path to achieve low a thermal resistance.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 30, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Junpeng Shi, Pei-Song Cai, Hao Huang, Zhenduan Lin, Chih-Wei Chao, Chen-Ke Hsu
  • Patent number: 10355004
    Abstract: A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Sangwoo Pae, Hagju Cho
  • Patent number: 10283590
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10283681
    Abstract: A phosphor-converted light emitting device includes a light emitting diode (LED) on a substrate, where the LED comprises a stack of epitaxial layers comprising a p-n junction. A wavelength conversion material is in optical communication with the LED. According to one embodiment of the phosphor-converted light emitting device, a selective filter is adjacent to the wavelength conversion material, and the selective filter comprises a plurality of nanoparticles for absorbing light from the LED not down-converted by the wavelength conversion material. According to another embodiment of the phosphor-converted light emitting device, a perpendicular distance between a perimeter of the LED on the substrate and an edge of the substrate is at least about 24 microns. According to another embodiment of the phosphor-converted light emitting device, the LED comprises a mirror layer on one or more sidewalls thereof for reducing light leakage through the sidewalls.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: May 7, 2019
    Assignee: Cree, Inc.
    Inventors: Brian T. Collins, Matthew Donofrio, Kevin W. Haberern, Bennett Langsdorf, Anoop Mathew, Harry A. Seibel, Iliya Todorov, Bradley E. Williams
  • Patent number: 10256329
    Abstract: A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising IniGa1-iAs with an Indium content i with a slope s1 and a second base layer on the emitter side comprising InjGa1-jAs with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising InmGa1-mAs with an Indium content m and a second base layer on the emitter side comprising InnGa1-nAs with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 9, 2019
    Assignee: Win Semiconductors Corp.
    Inventors: Shinichiro Takatani, Jui-Pin Chiu, Chia-Ta Chang
  • Patent number: 10249621
    Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Robert Visokay, Tae S. Kim, Mahalingam Nandakumar, Eric D. Rullan, Gregory B. Shinn
  • Patent number: 10249721
    Abstract: A semiconductor device includes a source trench extending into a semiconductor body from a first surface of the semiconductor body. A source trench dielectric and a source trench electrode are in the source trench. A gate trench dielectric and a gate trench electrode are in a gate trench extending into the semiconductor body from the first surface. A body region of a first conductivity type is between the gate and source trenches. A source region of a second conductivity type different from the first conductivity type is between the gate and source trenches. An interconnection electrically couples the body region and the source trench electrode. The interconnection adjoins a lateral face of the source trench electrode and the body region. A source contact is on the source trench electrode at the first surface.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 10236214
    Abstract: A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10224463
    Abstract: An object of the present invention is to provide a film formation technique having high productivity by realizing a foundation layer having excellent crystallinity with a small film thickness of about 2 ?m. An embodiment of the present invention relates to a film forming method which includes the step of forming a buffer layer by sputtering on a sapphire substrate held by a substrate holder. The buffer layer includes an epitaxial film having a wurtzite structure prepared by adding at least one substance selected from the group consisting of C, Si, Ge, Mg, Zn, Mn, and Cr to AlxGa1?xN (where 0?x?1).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 5, 2019
    Assignee: CANON ANELVA CORPORATION
    Inventor: Yoshiaki Daigo
  • Patent number: 10211058
    Abstract: An electrostatic discharge protection device includes a buried layer having a plurality of heavily doped regions of a first conductivity type and a laterally diffused region between adjacent heavily doped regions, a semiconductor region over the buried layer, and a first well of the first conductivity type extending from a surface of the semiconductor region to a heavily doped region. The device includes a first transistor in the semiconductor region having an emitter coupled to the first terminal, and a second transistor in the semiconductor region having an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jean-Phillippe Laine, Patrice Besse, Changsoo Hong, Rouying Zhan
  • Patent number: 10192753
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Sonehara, Takahiro Hirai, Masaaki Higuchi, Takashi Shimizu
  • Patent number: 10177187
    Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Jhy-Jyi Sze, Dun-Nian Yaung, Chen-Jong Wang, Yimin Huang, Yuichiro Yamashita
  • Patent number: 10170332
    Abstract: A method and structure for protecting high-mobility materials from exposure to high temperature processes includes providing a substrate having at least one fin extending therefrom. The at least one fin includes a dummy channel and source/drain regions. A dummy gate stack is formed over the dummy channel. A first inter-layer dielectric (ILD) layer is formed on the substrate including the fin. The first ILD layer is planarized to expose the dummy gate stack. After planarizing the first ILD layer, the dummy gate stack and the dummy channel are removed to form a recess, and a high-mobility material channel region is formed in the recess. After forming the high-mobility material channel region, contact openings are formed within a second ILD layer overlying the source/drain regions, and a low Schottky barrier height (SBH) material is formed over the source/drain regions.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10163892
    Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michel J. Abou-Khalil, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 10157989
    Abstract: A method of manufacturing a graphene electronic device may include forming a metal compound layer and a catalyst layer on a substrate, the catalyst layer including a metal element in the metal compound layer, growing a graphene layer on the catalyst layer, and converting the catalyst layer into a portion of the metal compound layer.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Seung Lee, Sang Wook Kim, Seong Jun Park, David Seo, Young Jun Yun, Yung Hee Lee
  • Patent number: 10153366
    Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 11, 2018
    Assignee: Polar Semiconductor, LLC
    Inventors: Thomas S. Chung, Noel Hoillien, Peter N. Manos, Steven Kosier
  • Patent number: 10134727
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Gerhard Schrom, Valluri R. Rao, Robert S. Chau
  • Patent number: 10134913
    Abstract: Disclosed is a method of manufacturing an a-IGZO TFT-based transient semiconductor. The method includes (a) stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer; (b) forming a PECVD layer on the nickel thin layer; (c) patterning the PECVD layer after setting a gate area and depositing a metallic layer; (d) lifting off the metallic layer to form a gage metallic thin layer and depositing a gage insulating layer on the gate metallic thin layer; (e) depositing an a-IGZO layer on the gate insulating layer; (f) etching an active area and the gate insulating layer; (g) forming a source electrode and a drain electrode and attaching a thermal release tape on the source electrode and the drain electrode; (h) delaminating the nickel thin layer; (i) performing transcription on a polyvinyl alcohol thin layer after etching the nickel thin layer; and (j) detaching the tape.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 20, 2018
    Assignee: INCHEON UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventor: Sung-Hun Jin