Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface, the light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second surface opposing the first surface; a p-side electrode; an n-side electrode; a p-side pillar; an n-side pillar; a first insulating layer; an optical layer; a second insulating layer; a first layer; a p-side interconnect; and an n-side interconnect. The first layer includes a first lower end portion and a second lower end portion.

Abstract: A thin film transistor (TFT) includes a hole transport layer having a first side and a second side and an electron transport layer having a first side and a second side. The first side of the electron transport layer is directly interfaced to the second side of the hole transport layer. The electron transport layer includes a material having greater ionization potential and greater electron affinity than the hole transport layer, thereby forming a hole barrier and an electron barrier at the junction between the electron transport layer and the hole transport layer. A channel in the TFT is created by current injected into the electron transport layer from a gate electrode rather than by an electrostatic field generated by voltage applied to the gate electrode. The accumulated charge density in the channel of the TFT can be significantly larger than what can be generated through field effect principle, therefore a much lower gate voltage is needed than in a conventional TFT.

Abstract: A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage.

Abstract: There is provided a semiconductor light emitting device including: a first conductivity-type semiconductor base layer; a mask layer disposed on the first conductivity-type semiconductor base layer and including a graphene layer with a plurality of openings exposing the first conductivity-type semiconductor base layer; and a plurality of light emitting nanostructures disposed on the openings and each including a first conductivity-type semiconductor core, an active layer, and a second conductivity-type semiconductor layer.

Abstract: A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure.

Abstract: To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This localized planarization, which is often carried out in a localized planarization station downstream of a CMP station, applies localized planarization to less than the entire face of the wafer to correct localized non-planar features. Other systems and methods are also disclosed.

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein.

Abstract: There is provided a solid state imaging element including: an insulation film laminated on a semiconductor substrate; a lower transparent electrode film formed and separated by the insulation film per pixel; a hydrophobic treatment layer laminated on a flat surface of the insulation film and the lower transparent electrode film; an organic photoelectric conversion layer laminated on the hydrophobic treatment layer; and an upper transparent electrode film laminated on the organic photoelectric conversion layer. Also, there is provided a production method thereof and an electronic device.

Abstract: The present disclosure provides various embodiments of light emitting chips and packages with improved current spreading structures, such as non-uniform via structures or varied via structures. In some embodiments, these structures may be used to regulate current flow and current crowding in order to improve emitter efficiency and uniformity. Some embodiments of this disclosure may also refer to contact pad placement to improve current flow. In some embodiments of non-uniform via structures, the size of the vias may vary, whereas in other embodiments, the shape or spacing between the vias may vary.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate.

Abstract: The present invention relates to an LED structure having a progressive work function layer, which adopts a conversion layer with a gradually varying work function as the medium for forming an Ohmic contact between the p-type GaN and the metal reflection layer. The work function of the conversion layer is not a single value. Instead, different quantities of dopants are doped at different depths of the conversion layer. Thereby, the conversion layer can match excellently the connected p-type GaN and the metal reflection layer. By taking advantage of the high light transmissivity of the material of the conversion layer, the possibility that light is absorbed by the Ohmic contact layer is reduced. The conversion according to the present invention can also block diffusion of the metal in the metal reflection to the p-type GaN. Accordingly, it can be used as both an Ohmic contact layer and a barrier layer.

Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

Abstract: In one embodiment, a method includes depositing a CZT(S, Se) precursor layer onto a substrate, introducing a source-material layer comprising Sn(S, Se) into proximity with the precursor layer, and annealing the precursor layer in proximity with the source-material layer in a constrained volume.

Abstract: Semiconductor power devices such as vertical FPMOS are described preferably having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches with controlled spacing between their surfaces to achieve increased capacitance between them at increasing depth from the top surface. This provides higher frequency performance at higher power levels while improving tolerance to higher voltage.

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, a drain electrode, a first protective layer, and a second protective layer. The gate electrode is disposed on a substrate. The metal oxide semiconductor layer is disposed on a gate insulating layer and electrically connects the source electrode and the drain electrode. The first protective layer disposed on the metal oxide semiconductor layer has a first oxygen vacancy concentration. The second protective layer disposed on the first protective layer has a second oxygen vacancy concentration. A boundary area located between the first and second protective layers has a third oxygen vacancy concentration. The third oxygen vacancy concentration is respectively greater than the first oxygen vacancy concentration and the second oxygen vacancy concentration.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.