Abstract: Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

Abstract: A multi-layered contact to a semiconductor structure and a method of making is described. In one embodiment, the contact includes a discontinuous Chromium layer formed over the semiconductor structure. A discontinuous Titanium layer is formed directly on the Chromium layer, wherein portions of the Titanium layer extend into at least some of the discontinuous sections of the Chromium layer. A discontinuous Aluminum layer is formed directly on the Chromium layer, wherein portions of the Aluminum layer extend into at least some of the discontinuous sections of the Titanium layer and the Chromium layer.

Abstract: In one example, a field effect transistor includes a fin. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is wrapped around the conducting channel, between the source/drain regions. In another example, a method for fabricating a field effect transistor includes forming a fin on a wafer. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is also formed between the source/drain regions and wraps around the conducting channel.

Abstract: Embodiments of the disclosure provide a thin film transistor and a fabrication method thereof, an array substrate and a display. The thin film transistor comprises a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The active layer comprises a first active layer and a second active layer; and the first active layer is arranged close to the gate insulating layer, and the second active layer is arranged close to the source electrode and the drain electrode. A carrier mobility of the first active layer is greater than that of the second active layer.

Abstract: A method of manufacturing a display apparatus includes separating a light-emitting diode (“LED”) chip from a base substrate; disposing the separated light-emitting diode chip in a solution; disposing a substrate including a first electrode thereon, in the solution; with the separated light-emitting diode chip and the substrate including the first electrode thereon in the solution, applying a negative voltage to the substrate to attract the separated light-emitting diode chip to the first electrode on the substrate; mounting the light-emitting diode chip attracted to the first electrode, on the first electrode; and removing the substrate with the light-emitting diode chip mounted on the first electrode from the solution and drying the removed substrate, to form the display apparatus.

Abstract: According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.

Abstract: A bonding device and bonding method for bonding an FPC film on a display panel through an anisotropic conductor attached to the display panel, the device including a panel supporting unit configured to support the display panel; a heating and pressurizing unit disposed on an upper area of the panel supporting unit and configured to pressurize and heat a compression area of the FPC film placed on an upper part of the anisotropic conductor towards the display panel, a film supporting unit disposed adjacent the panel supporting unit and configured to support the FPC film, and a film pre-heating unit provided in the film supporting unit and configured to pre-heat the FPC film.

Abstract: A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact.

Abstract: A method for manufacturing a semiconductor device include forming a dielectric layer over an underlying layer; forming an etch barrier over the dielectric layer, wherein a partial via opening is formed in the etch barrier and exposes a lower portion of the etch barrier; forming an assist-etch barrier over the etch barrier to fill the partial via opening; patterning the assist-etch barrier to form an initial trench opening in the assist-etch barrier, wherein the initial trench opening communicates with the partial via opening; patterning the lower portion of the etch barrier exposed by the partial via opening to form a final via opening in the etch barrier; patterning the dielectric layer exposed by the final via opening to form an initial via hole in the dielectric layer; patterning the etch barrier exposed by the initial trench opening to form a final trench opening in the etch barrier; patterning a lower portion of the dielectric layer exposed by the initial via hole to form a final via hole in the dielectr

Abstract: A method of fabricating a semiconductor device includes etching a stack of first-material layers and second-material layers alternately disposed one on another on a substrate. An upper portion of the stack is etched using an end point detection (EPD) signal of an etching reaction gas, and a function of an injection time of an etchant with respect to a depth of an opening is obtained while the upper portion of the stack is etched. A lower portion of the stack is etched using the obtained function.

Abstract: A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole layer of opposite polarity relative to the polarity of the fin and reduces source to drain leakage. A semiconductor structure may include a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor layer, a gate electrode on the semiconductor layer, a first insulating layer between the semiconductor layer and the gate electrode; a second insulating layer on the gate electrode, source and drain electrodes corresponding to both ends of the semiconductor layer and disposed on the second insulating layer, and a doping layer disposed along contact holes of the first and second insulating layers, which expose the both ends of the semiconductor layer, such as, between the both ends of the semiconductor layer and the source and drain electrodes.

Abstract: An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered.

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

Abstract: A semiconductor substrate is a provided and an insulating layer is formed thereon. A cavity structure is formed above the insulating layer, including a lateral growth channel and a fin seed structure arranged in the lateral growth channel. The fin seed structure provides a seed surface for growing a fin structure. One or more first semiconductor structures of a first semiconductor material and one or more second semiconductor structures of a second, different, semiconductor material are grown sequentially in the growth channel from the seed surface in an alternating way. The first semiconductor structures provide a seed surface for the second semiconductor structures and the second semiconductor structures provide a seed surface for the first semiconductor structures. The second semiconductor structures are selectively etched, thereby forming the fin structure comprising a plurality of parallel fins of the first semiconductor structures. Corresponding semiconductor structures are also included.

Abstract: The present invention provides a manufacture method of a thin film transistor substrate. In the same photolithographic process, the via deposing process is implemented to the gate isolation layer and the etching stopper layer is patterned. That is, the photolithographic process is not implemented but the oxide semiconducting pattern is formed directly after the gate isolation layer is formed. After the etching stopper layer is formed, the gate isolation layer and the etching stopper layer are patterned in the same photolithographic process. Comparing with the manufacture method of prior art, one photolithographic process can be eliminated. Meanwhile, the aperture ratio is raised by forming an open at the transparent conducting layer.

Abstract: A method for manufacturing an eye-protecting liquid crystal display device is disclosed, in which an ultraviolet light emitting material and a ultraviolet absorbent are added in a first planarization layer of an array substrate and a second planarization layer of a color filter substrate. The ultraviolet absorbent absorbs short-wavelength blue light having a wavelength less than 400 nm and ultraviolet light emitting from a backlight module. The short-wavelength blue light and the ultraviolet light so absorbed excite the ultraviolet light emitting material to give off long-wavelength visible blue light having a wavelength greater than 400 nm. The first and second planarization layers are thus useful in converting ultraviolet light and short-wavelength blue light having a wavelength less than 400 nm, which could damage human eyes, into long-wavelength visible blue light having a wavelength greater than 400 nm that does not damage human eyes.

Abstract: A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.

Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.

Abstract: A semiconductor device includes a semiconductor substrate; a first semiconductor region that includes an extension portion extending in a specific direction at a specific width as viewed along a direction orthogonal to the main surface; a second semiconductor region that is shaped to include a portion running along the extension portion of the first semiconductor region as viewed along the direction orthogonal to the main surface; a field relaxation layer that relaxes a field generated between the first semiconductor region and the second semiconductor region, that is formed on the second semiconductor region side of the main surface, and that is formed by a semiconductor layer; and a conductor that is connected to the second semiconductor region, and that has an end portion on the first conductor region side positioned within the range of the field relaxation layer.